Display Panel Support Pillar Contact Area and GOA Impedance
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Solution Overview
Problem
8K ultra-high-resolution electronic devices face issues with support pillars easily peeling off and impedance differences causing output signal variations due to small contact areas and CK signal impedance discrepancies.
Innovation Solution
A display panel design with a protrusion-depression pattern on the contact layer to increase the contact area between support pillars and the substrate, and a circuit structure with adjusted voltage drop values for clock input transistors to compensate for impedance differences across GOA units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the contact area between support pillar and bottom layer is reduced to accommodate higher resolution, then the number of pixels increases, but the support pillar easily peels off from the bottom layer
Solution Approach 1:
The contact layer is divided into multiple protrusions and depressions, creating a segmented contact interface between the support pillar and bottom layer. This segmentation increases the effective contact area without increasing the overall footprint, thereby preventing support pillar peeling while maintaining high resolution pixel density.
Solution Approach 2:
The contact interface is extended from a two-dimensional planar contact to a three-dimensional structured contact with protrusions and depressions. This dimensional change increases the contact area and mechanical interlocking without occupying additional lateral space, solving the peeling issue in high-resolution displays.
2Measurement precision
If the number of GOA units increases to achieve ultra-high resolution, then the resolution improves, but the impedance difference between clock signal lines increases causing output signal variation
Solution Approach 1:
Different voltage drop values are applied to clock input transistors in different GOA units based on their specific positions and impedance characteristics. This localized adjustment compensates for impedance differences caused by varying clock signal line lengths, ensuring consistent output signals across all 4320 rows of GOA units in the 8K display.
Solution Approach 2:
The patent implements a feedback mechanism where the impedance characteristics of each clock signal line are measured and used to determine the appropriate voltage drop value for the corresponding clock input transistor. This feedback loop ensures that signal variations are compensated, maintaining uniform output across the ultra-high resolution display.
Data Source
AI summary
The present disclosure provides a display panel and an electronic device. In the display panel, a contact area between a support pillar and a bottom layer is increased, without changing a size of a single sub-pixel, thereby alleviating a technical problem that the support pillar easily peels off in an existing 8K ultra-high-resolution electronic device. Moreover, by adjusting voltage drop values of clock input transistors in different GOA units, the voltage drop value between each of the GOA units and clock driving chips is approximately the same.