Display Panel Pin Layout With Non-Signal Buffers for Signal Integrity
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Solution Overview
Problem
In flexible wearable devices, the small size of display panels leads to high voltages and large voltage differences between adjacent pins, increasing the risk of short circuits and signal inaccuracies, particularly in unilaterally-driven signal routing solutions.
Innovation Solution
Incorporating non-signal pins between selected adjacent signal pins to maintain uniform pin spacing and voltage thresholds, thereby reducing the risk of short circuits and ensuring signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the display panel size is reduced for flexible wearable devices, then the portability and wearability are improved, but the voltage between adjacent pins increases and voltage differences become larger, increasing the risk of short circuits and signal inaccuracies
Solution Approach 1:
A non-signal pin is introduced as an intermediary element between adjacent signal pins with high voltage or large voltage differences. This non-signal pin acts as a physical and electrical buffer, increasing the spacing between high-voltage signal pins and reducing the risk of short circuits and signal interference, thereby maintaining signal integrity in miniaturized display panels
Solution Approach 2:
The patent applies local quality by selectively placing non-signal pins only between specific adjacent signal pins that have high voltage or large voltage differences, rather than uniformly across all pin pairs. This targeted approach optimizes the prevention of short circuits and signal inaccuracies while minimizing the impact on overall pin density and display panel size
2Reliability
If non-signal pins are added between adjacent signal pins, then the short circuit risk and signal inaccuracy are reduced, but the pin density decreases and the binding region area increases
Solution Approach 1:
Non-signal pins are selectively placed only between signal pins that have high voltage or large voltage differences, rather than uniformly across all adjacent pin pairs. This targeted placement minimizes the increase in binding region area while effectively preventing short circuits and signal inaccuracies in critical locations
Solution Approach 2:
The patent changes the electrical parameters (voltage levels and voltage differences) as the basis for determining where to place non-signal pins. By analyzing the voltage characteristics of adjacent signal pins, the patent dynamically adjusts the pin arrangement to place non-signal buffers only where electrical parameters indicate a risk of short circuits or signal interference
Data Source
AI summary
A display panel, a circuit board and a display device are provided, belonging to the field of displays. The display panel has a display region and a binding region which is on at least one side of the display region, and the display panel includes: a substrate; a plurality of signal pins on the substrate and in the binding region, the signal pins being arranged at intervals in a first direction and being connected to the circuit board; and at least one non-signal pin on the substrate and between two adjacent signal pins.