Display Panel Pixel Circuit Layout for Reduced Gate-Line Coupling
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Solution Overview
Problem
The existing pixel driving circuits using LTPO technology face issues with insufficient data signal writing due to coupling effects between gate lines and connecting parts, leading to inefficiencies in display panel performance.
Innovation Solution
The proposed display panel design includes a pixel driving circuit with a specific arrangement of conductive and active layers, where the orthographic projections of gate lines and connecting parts are positioned to avoid overlap, reducing the coupling effect and improving data signal writing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate lines and connecting parts are arranged in conventional overlapping positions, then device complexity is reduced, but coupling effects occur causing insufficient data signal writing
Solution Approach 1:
The patent applies dimensionality change by adjusting the spatial arrangement of conductive layers. Specifically, the first connecting part is positioned in the fourth conductive layer while the first conductive part is in the first conductive layer, creating vertical separation between components that were previously arranged horizontally in the same layer. This multi-layer stacking approach eliminates coupling effects between gate lines and connecting parts while maintaining compact device footprint.
2Productivity
If orthographic projections of gate lines and connecting parts overlap, then area utilization is improved, but coupling effects reduce data signal writing
Solution Approach 1:
The patent resolves the area efficiency contradiction by transitioning from two-dimensional planar arrangement to three-dimensional multi-layer stacking. The first connecting part is placed in the fourth conductive layer above the first conductive layer containing the first conductive part, allowing vertical integration that maintains high area utilization while eliminating harmful coupling effects through layer separation.
3Reliability
If conventional LTPO pixel driving circuit layout is used, then manufacturing process is simplified, but coupling effects cause performance degradation
Solution Approach 1:
The patent applies segmentation by dividing the circuit components into distinct conductive layers: the first conductive part (forming gate electrode of driving transistor) is separated from the first connecting part (connecting to first electrode of first and second transistors) by placing them in different conductive layers (first vs. fourth layer). This segmentation eliminates coupling effects between gate lines and connecting parts while maintaining manufacturability through standardized multi-layer TFT processes.
Data Source
AI summary
A display panel including a pixel driving circuit including a driving transistor, a first transistor having a gate electrode connected to a first gate line and a first electrode connected to a gate electrode of the driving transistor, and a second transistor having a gate electrode connected to a second gate line, a first electrode connected to the gate electrode of the driving transistor, and a second electrode connected to a second electrode of the driving transistor, the driving transistor is a P type transistor, and the first transistor and the second transistor are N type transistors, wherein the display panel further includes: a base substrate, a first conductive layer, a third conductive layer, and a first conducting part.