Display Panel Planarization Layer for Step Difference Compensation
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Solution Overview
Problem
As liquid crystal display devices increase in size and resolution, the thickness of gate lines is increased to reduce electrical line resistance, leading to step differences in the thin film transistor substrate, necessitating an improved low line electrical resistance structure and manufacturing process.
Innovation Solution
A method of manufacturing a display panel involving sequential stacking of layers, including a first metal layer, insulating layer, amorphous silicon layer, and photoresist layers, with patterning using masks to form a planarization layer that compensates for step differences and reduces manufacturing complexity, allowing for a wider material selection for the planarization layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness of gate lines is increased to reduce electrical line resistance, then electrical line resistance is reduced, but step differences are generated in the thin film transistor substrate
Solution Approach 1:
A planarization layer is introduced as an intermediary component between the substrate and the gate line. This planarization layer has a greater thickness than the gate line thickness, allowing the gate line to be formed with increased thickness for lower resistance while the planarization layer compensates for the step difference it creates, maintaining a flat surface for subsequent processing steps.
2Ease of manufacture
If the planarization layer is formed before the active layer at high temperature, then the manufacturing process is simplified, but the material selection for the planarization layer is limited
Solution Approach 1:
The planarization layer is formed after the active layer is created through high-temperature processing. This sequencing allows the use of organic materials for the planarization layer that would be incompatible with high-temperature processes, thereby expanding material selection flexibility while maintaining process simplicity.
Data Source
AI summary
A display panel includes a gate electrode and a gate line on a substrate, a gate insulating layer and an active layer sequentially on the gate electrode and the gate line, a planarization layer which is on the substrate and compensates for a step difference between the substrate, and the gate electrode and the gate line, respectively, source and drain electrodes on the active layer overlapping the gate electrode and spaced apart from each other, a data line on the active layer and crossing the gate line, a protective layer which covers the planarization layer, the source and drain electrodes, and the data line, a contact hole defined in the planarization layer and partially exposing the drain electrode, and a pixel electrode on the protective layer and electrically connected to the drain electrode through the contact hole.