Display Panel Power Line Layout for Narrower Borders
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Solution Overview
Problem
Display panels have wide borders due to the layout of power lines that bypass cell test units, leading to increased resistance and poor display effects.
Innovation Solution
The display panel design includes a first power line that passes through the area where the cell test unit is disposed, with a second sub-connecting line between adjacent thin-film transistors, reducing the space occupied in the non-display region and minimizing resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the power line bypasses the cell test unit, then the cell test unit can be properly isolated, but the border width increases and resistance increases
Solution Approach 1:
The power line is divided into two separate sub-connecting lines: a first sub-connecting line that extends from the light-emitting device to the cell test unit, and a second sub-connecting line that extends from the cell test unit to the power supply. This segmentation allows the power line to pass through the cell test unit area without requiring a wide bypass, thereby reducing border width while maintaining proper isolation.
Solution Approach 2:
The power line routing is changed from a two-dimensional bypass around the cell test unit to a routing that utilizes the vertical dimension by passing through different layers. The first sub-connecting line is disposed above the cell test unit in a first layer, while the second sub-connecting line is disposed below the cell test unit in a second layer, allowing the power line to pass through the cell test unit area without increasing border width.
2Reliability
If the power line bypasses the cell test unit, then the cell test unit can be properly isolated, but the resistance increases
Solution Approach 1:
The power line is segmented into two sub-connecting lines that pass through the cell test unit area rather than bypassing it. This reduces the total length of the power line, thereby reducing resistance and energy loss while maintaining proper isolation through the layered structure.
Solution Approach 2:
By routing the power line through different layers (first sub-connecting line above the cell test unit, second sub-connecting line below), the path length is reduced compared to a bypass route, thereby reducing resistance and energy loss.
3Length of stationary object
If the power line passes through the cell test unit area, then the border width is reduced, but the test signal line routing becomes complex
Solution Approach 1:
The test signal line is routed through a different layer (third layer) than the power line (first and second layers). This vertical separation in the third dimension simplifies the routing complexity by avoiding conflicts between power and signal lines, while still allowing the power line to pass through the cell test unit area to reduce border width.
4Length of stationary object
If the power line passes through the cell test unit area, then the border width is reduced, but the layer structure becomes complex
Solution Approach 1:
The power line is segmented into two sub-connecting lines disposed in different layers (first layer and second layer), with the cell test unit located between them. This segmentation allows the power line to pass through the cell test unit area efficiently, reducing border width while organizing the layer structure in a systematic manner.
Solution Approach 2:
The layered structure utilizes the vertical dimension to route different signal lines at different heights. The first sub-connecting line is in a first layer above the cell test unit, the second sub-connecting line is in a second layer below the cell test unit, and the test signal line is in a third layer, creating an organized three-dimensional routing that reduces border width while managing complexity.
Data Source
AI summary
Provided is a display panel, including a substrate provided with a display region and a non-display region; a light-emitting device disposed in the display region; a cell test unit disposed in the non-display region, wherein the cell test unit include thin-film transistors arranged along a first direction; a first power line disposed in the non-display region, wherein the first power line includes a first sub-connecting line and a second sub-connecting line, the first sub-connecting line is disposed between the cell test unit and the display region and is electrically connected to the light-emitting device, one end of the second sub-connecting line is electrically connected to the first sub-connecting line, and the other end of the second sub-connecting line is disposed on a side, distal to the display region, of the cell test unit, and the second sub-connecting line is disposed between adjacent thin-film transistors in the first direction.