Display Panel Scan-Line Pull-Down Layout for Faster Falling Edges
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Solution Overview
Problem
Traditional display panels face issues with long falling edge times of scan signals and low aperture ratios due to increased refresh frequencies, leading to display abnormalities and reduced visual performance.
Innovation Solution
A display panel design featuring a pull-down transistor with a low potential wiring and control wiring strategically placed between data lines, allowing for quicker falling edge response and increased aperture ratio through efficient layout optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the refresh frequency is increased to improve display smoothness and visual experience, then the visual performance is improved, but the falling edge time of scan signals becomes longer causing display abnormalities
Solution Approach 1:
The patent extracts the scan signal falling edge delay problem from the overall scan process by introducing a dedicated pull-down transistor that operates independently to force the scan signal to ground potential, separating the turn-on and turn-off functions of the scan signal control
Solution Approach 2:
The pull-down transistor acts as an intermediary component between the scan signal line and ground, mediating the falling edge transition by providing a controlled path to discharge the line load capacitance, thereby resolving the delay caused by direct capacitive coupling
2Speed
If the turn-on time of scan pulse is shortened to support higher refresh frequency, then the refresh frequency capability is improved, but the falling edge cannot reach ideal potential causing write transistor to remain in on state
Solution Approach 1:
The patent applies preliminary anti-action by pre-positioning the pull-down transistor to actively counteract any residual charge or potential on the scan signal line before the write transistor needs to switch, ensuring the scan signal is firmly at ground potential and preventing unintended transistor conduction
Solution Approach 2:
The pull-down transistor provides feedback control by continuously monitoring and maintaining the scan signal line at ground potential during the off period, ensuring that any potential drift or residual charge is immediately corrected to prevent write transistor malfunction
3Area of stationary object
If the display area layout is optimized to reduce space usage, then the aperture ratio is improved, but the falling edge time of scan signals increases
Solution Approach 1:
The patent transitions from planar layout optimization to three-dimensional circuit design by introducing a pull-down transistor that operates in a different spatial dimension (vertical stacking or lateral placement in display pixel structure), allowing space-efficient implementation without compromising falling edge performance
Solution Approach 2:
The pull-down transistor is nested within the existing pixel circuit structure, utilizing available space in the display pixel layout to house the additional component, thereby minimizing the impact on aperture ratio while achieving the desired electrical performance
Data Source
AI summary
The present application discloses a display panel and a display device. The display panel includes an active layer, a gate layer, and a metal layer, which is able to quickly pull down a falling edge of a scan signal in a first scan line when a rising edge of a scan signal in a second scan line arrives. By constructing a low-potential wiring, a control wiring, and a pull-down transistor between the first data line and the second data line, a layout with less space can be completed and an aperture ratio can be increased as much as possible.