Display Panel Cascaded Shift Registers for Complete Scan Pulse Control
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Solution Overview
Problem
Conventional scan driver circuits in display panels often provide abnormal drive signals to pixel circuits, leading to abnormal displays due to incomplete scan pulse signals caused by the independent nature of scan pulse and control signals, resulting in regions of the screen failing to function properly.
Innovation Solution
A display panel with a driver circuit featuring cascaded shift registers, each equipped with a first and second control portion, ensures that the second output signal is an effective pulse only when the first output signal's time period overlaps with the frequency control signal's effective pulse, preventing incomplete pulse signals and maintaining normal pixel circuit operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional scan driver circuits are used with independent scan pulse and control signals, then the device complexity is reduced, but the reliability of drive signals deteriorates causing abnormal displays
Solution Approach 1:
The patent merges the scan pulse signal and control signal generation into a unified shift register system. The shift register generates both signals in a coordinated manner, ensuring that scan pulse signals are only output when corresponding control signals are active. This integration eliminates the independence issue between scan pulse and control signals, preventing abnormal displays while maintaining reasonable circuit complexity.
2Productivity
If scan pulse signals are generated independently without time period verification, then the productivity of signal generation is improved, but the manufacturing precision of display quality deteriorates
Solution Approach 1:
The shift register performs preliminary verification of time periods before outputting scan pulse signals. It checks whether the time period of each scan pulse signal falls within the effective time period of corresponding control signals. This preliminary action ensures that only valid scan pulse signals are generated and output, maintaining high productivity while ensuring display quality precision.
3Ease of operation
If the shift register outputs all generated scan pulse signals without verification, then the ease of operation is improved, but the loss of information increases due to incomplete pulse signals
Solution Approach 1:
The shift register implements a feedback mechanism where the control signal status is continuously monitored and used to regulate scan pulse signal output. The circuit compares the time period of generated scan pulse signals with the effective time period of control signals, and only outputs signals that pass this verification. This feedback control prevents information loss while maintaining simple operation.
Data Source
AI summary
A display panel includes a driver circuit including shift registers with N stages and being cascade with each other, where N≥2, and each shift register includes a first control portion and a second control portion. The first control portion is configured to control a first output signal, where the first output signal of an i-th stage of shift register is an input signal of a j-th stage of shift register, and 1≤i≤N, 1≤j≤N. The second control portion is configured to receive at least the first output signal and a frequency control signal and control a second output signal. In a case where the first output signal is an effective pulse and a time period of the effective pulse is within a time period of an effective pulse of the frequency control signal, the second output signal is the effective pulse.