Display Panel Gate Insulator Layout for Fewer Masks and Reliable Contacts
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing display panel manufacturing process is costly and complex, requiring multiple masks, which complicates the production and can lead to reliability issues due to blocking of current paths and increased resistance in transistor areas.
Innovation Solution
A display panel design featuring a gate insulating pattern layer with a thin first portion and a thicker second portion, where the first portion is in contact with the source or drain areas, and connection electrodes on the same layer as the gate electrode, formed using a method involving photoresist layers, dry etching, and ashing processes to prevent current path blocking and increase resistance, thereby simplifying the manufacturing process while enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a mask-based manufacturing process is used to form the gate insulating layer and contact holes, then manufacturing precision is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent combines the formation of the gate insulating layer and contact holes into a single etching process. The gate insulating layer includes a first portion and a second portion with different thicknesses, where the first portion is etched to form contact holes while the second portion remains as the gate insulating layer. This merging eliminates the need for separate masking steps for each structure, reducing process complexity while maintaining precision.
Solution Approach 2:
The gate insulating layer is designed with local quality variations, having a first portion with a specific thickness for contact hole formation and a second portion with a different thickness for gate insulation. This local differentiation allows the same layer to serve multiple functions, reducing the number of separate layers and masks needed, thereby simplifying the manufacturing process while maintaining the required precision for each function.
2Reliability
If the gate insulating layer is made thin to reduce resistance, then electrical conductivity is improved, but reliability deteriorates due to current path blocking
Solution Approach 1:
The gate insulating layer is designed with different thicknesses in different regions: the first portion has a thickness optimized for forming contact holes and ensuring proper electrical connection, while the second portion has a different thickness for effective gate insulation. This local quality differentiation allows the structure to simultaneously prevent current path blocking in the contact region while maintaining proper insulation in the gate region, thereby improving overall electrical reliability.
Solution Approach 2:
The gate insulating layer is segmented into a first portion and a second portion with different thicknesses. The first portion is specifically designed to be etched away to form contact holes, ensuring proper electrical connection to the semiconductor pattern, while the second portion maintains the necessary insulation thickness. This segmentation allows each portion to optimize its function, preventing both current path blocking and excessive resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents current path blocking and increases resistance in the source and drain areas, resulting in a more reliable and cost-effective display panel manufacturing process with improved circuit layer reliability.
Implementation Method 1
forming a gate insulating pattern layer with a first portion and a second portion
Implementation Method 2
involving photoresist layers, dry etching, and ashing processes
Implementation Method 3
involving photoresist layers, dry etching, and ashing processes
Data Source
Figure 1
Figure 2A
Figure 2B
AI summary
A display panel includes a base substrate, a transistor disposed on the base substrate and including a semiconductor pattern including a source area, a drain area, and an active area, a gate insulating pattern layer disposed on the semiconductor pattern, and a gate electrode disposed on the gate insulating pattern, and connection electrodes disposed on the gate insulating pattern layer and connected to the semiconductor pattern through contact holes, respectively. The gate insulating pattern layer includes a first portion overlapping at least one of the source area and the drain area and a second portion extending from the first portion. A thickness of the first portion is equal to or smaller than about 50% of a thickness of the second portion.