Display Panel Pixel Circuit with Split PAM and PWM Reset Voltages

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Solution Overview

Problem

Existing driver circuits for high-resolution display panels, such as micro LED and OLED panels, suffer from irrational design due to the use of uniform reset voltages for both pulse amplitude modulation (PAM) and pulse width modulation (PWM) circuits, failing to meet the distinct requirements of each circuit.

Innovation Solution

Differentially setting the voltage values of reset signals for the amplitude modulation and pulse width modulation circuits, ensuring Vref1≠Vref2, allows for independent and flexible adjustment of reset voltages to meet the specific requirements of each circuit, thereby improving design rationality.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If uniform reset voltages are used for both PAM and PWM circuits, then the circuit design is simplified, but the functional requirements of each circuit cannot be met

Engineering Contradiction:
Improvecircuit design complexityVSAvoidcircuit functional performance
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent applies local quality by assigning different reset voltages (Vref1 for PAM circuit, Vref2 for PWM circuit) to different circuits based on their specific functional requirements. This allows each circuit to operate with optimized parameters while maintaining overall system functionality.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the voltage parameter of reset signals from a uniform value to different values (Vref1≠Vref2) for different circuits. This parameter differentiation enables each circuit to achieve optimal performance according to its specific modulation requirements.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If different reset voltages are used for PAM and PWM circuits, then the functional requirements of each circuit are met, but the circuit design becomes more complex

Engineering Contradiction:
Improvecircuit functional performanceVSAvoidcircuit design complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the reset signal generation by creating separate reset signal generation units for PAM and PWM circuits, each with its own dedicated reset voltage (Vref1 and Vref2 respectively). This segmentation allows independent optimization of each circuit while maintaining clear functional boundaries.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements a universal reset signal generation mechanism that can produce different voltage levels (Vref1 and Vref2) based on circuit requirements. This multi-functional approach allows a single design framework to accommodate different circuit needs without requiring completely separate systems.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20260024479A1Display panel and display device
Publication Date: 2026.01.22 TIANMA ADVANCED DISPLAY TECH INST (XIAMEN) CO LTD
  • US20260024479A1 patent drawing
  • US20260024479A1 patent drawing
  • US20260024479A1 patent drawing

AI summary

Provided are a display panel and a display device. The display panel includes pixel circuits and light-emitting elements. A pixel circuit of the pixel circuits includes an amplitude modulation circuit and a pulse width modulation circuit. The amplitude modulation circuit includes an amplitude driving sub-module and an amplitude reset sub-module. The amplitude reset sub-module is configured to transmit a first reset signal to a control terminal of the amplitude driving sub-module, and the voltage value of the first reset signal is Vref1. The pulse width modulation circuit includes a pulse width driving sub-module and a pulse width reset sub-module. The pulse width reset sub-module is configured to transmit a second reset signal to a control terminal of the pulse width driving sub-module, and voltage value of the second reset signal is Vref2, Vref1<Vref2.