Display Panel Signal Routing to Minimize Function-Region Bezels
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Solution Overview
Problem
Existing display devices require wider bezels around function regions to accommodate signal line connections, compromising the screen-to-body ratio due to the integration of components like front cameras and fingerprint recognition elements.
Innovation Solution
A display panel design with signal lines configured to minimize bezel area by connecting separated segments within the display region, reducing the need for winding around the function region and optimizing signal line placement to reduce parasitic capacitance and improve display uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If signal lines are routed around the function region to connect separated segments, then signal transmission is maintained, but the bezel area increases and screen-to-body ratio decreases
Solution Approach 1:
The patent introduces a third dimension by routing the third signal line through the display region (specifically through the first display sub-region) rather than confining all connections to the bezel area. This vertical/diagonal routing through the display region allows signal segments to connect without expanding the horizontal bezel footprint, effectively using dimensional transition to resolve the space conflict.
Solution Approach 2:
The patent divides the display region into multiple sub-regions (first display sub-region, second display sub-region) and strategically places different signal line segments in different sub-regions. This segmentation allows optimized routing paths for different signal lines, enabling the third signal line to connect separated segments through the first display sub-region while other signal lines are routed through the second display sub-region, thereby minimizing overall bezel area.
2Reliability
If signal lines are densely packed around the function region, then connection is achieved, but parasitic capacitance increases and display uniformity deteriorates
Solution Approach 1:
The patent applies different routing strategies to different signal lines based on their specific requirements. The third signal line is routed through the first display sub-region while the second signal line is routed through the second display sub-region. This localized optimization ensures that each signal line has an appropriate path that minimizes interference and parasitic capacitance while maintaining necessary connections.
Solution Approach 2:
By transitioning from two-dimensional bezel-area routing to three-dimensional routing that includes paths through the display region, the patent increases the available routing space. This dimensional expansion allows signal lines to be separated in the vertical/diagonal direction rather than being constrained to horizontal proximity in the bezel, thereby reducing parasitic capacitance and improving display uniformity.
3Ease of manufacture
If wider bezel is provided around function region, then signal line winding space is sufficient, but screen-to-body ratio is reduced
Solution Approach 1:
The patent resolves the manufacturing complexity issue by introducing routing paths through the display region (first and second display sub-regions), effectively using the vertical/diagonal dimension to provide adequate winding space without expanding the horizontal bezel area. This maintains screen-to-body ratio while ensuring sufficient space for signal line connections.
Solution Approach 2:
The patent segments the routing paths for different signal lines into different display sub-regions, allowing each signal line to have its own optimized path. This segmentation provides sufficient winding space for complex connections without requiring a uniformly wider bezel, thereby maintaining a high screen-to-body ratio while ensuring manufacturability.
Data Source
AI summary
Provided are a display panel and a display device. The display panel includes a first display region, a second display region and a first function region. The second display region includes a first signal line extending in the second direction and including a first segment and a second segment that are separated by the first function region. The first display region includes a first display sub-region. The first display sub-region includes a third signal line extending in the second direction and electrically connected to the first segment and the second segment. In the same pixel circuit of the first display sub-region, the second signal line and the third signal line are located on the same side of a fourth signal line.