Display Panel Layered Scan Driving Circuit for Compact Non-Display Regions
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Solution Overview
Problem
Existing display panels have a significant non-display region that occupies unnecessary space, which can be reduced by optimizing the layout and structure of the scan driving circuit.
Innovation Solution
The display panel incorporates a scan driving circuit with a reduced occupancy area by using a layered structure of semiconductor pattern layers and gate electrodes, connected through insulation layers and contact-holes, to efficiently manage scan signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a conventional scan driving circuit is used, then the display panel can be manufactured with standard processes, but the non-display region occupies excessive space
Solution Approach 1:
The patent applies dimensionality change by stacking multiple semiconductor pattern layers (first and second semiconductor pattern layers) and gate electrodes in the vertical dimension rather than expanding the circuit horizontally. The first and second transistors are formed with overlapping channel regions across different layers, allowing the scan driving circuit to achieve sufficient drive capability while maintaining a compact footprint in the non-display region.
Solution Approach 2:
The patent implements nesting by placing the second semiconductor pattern layer and second gate electrode overlying the first semiconductor pattern layer and first gate electrode, with the channel regions overlapping in the vertical projection. This nested configuration allows multiple transistor components to occupy the same horizontal footprint while being distinguished by their vertical layer positions, thereby reducing the overall area required for the scan driving circuit.
2Area of stationary object
If the scan driving circuit occupancy area is reduced, then the non-display region is minimized, but the transistor structure becomes more complex
Solution Approach 1:
The patent applies segmentation by dividing the transistor structure into distinct segments across multiple layers: the first semiconductor pattern layer forms the first transistor with source/drain regions and channel, while the second semiconductor pattern layer forms the second transistor with corresponding source/drain regions and channel. Each layer's transistor components are electrically connected through contact holes, allowing the complex multi-layer structure to be systematically assembled from simpler layered segments.
Solution Approach 2:
The patent implements multi-functionality by designing the first and second transistors to work together as a unified scan driving circuit. Both transistors share common electrical connections through contact holes and contribute to generating the scan signal output. The overlapping channel regions and shared gate electrode connections enable the circuit to perform multiple functions (signal generation, signal amplification, and output driving) within the compact structure formed by the two transistor layers.
Data Source
AI summary
A display panel includes a scan driving circuit. The scan driving circuit includes a first transistor that outputs a high-voltage of a scan signal during a turn-on period. The first transistor includes a first semiconductor pattern layer including a first input region, a first output region, and a first channel region, a first gate electrode overlapping the first channel region, a second semiconductor pattern layer including a second input region electrically connected to the first input region, a second output region electrically connected to the first output region, and a second channel region overlapping the first channel region, and a second gate electrode overlapping the second channel region, and electrically connected to the first gate electrode.