Display Panel Scan Line Sharing for Narrow Borders
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Solution Overview
Problem
Existing display panel technologies require two scan lines for each row of pixel circuits, leading to an increased number of scan lines and gate driving circuits, which complicates the realization of narrow borders due to space and cost constraints.
Innovation Solution
The display panel configuration includes a plurality of pixel circuits arranged in an array, where each scan line controls the charging of a corresponding row of pixel circuits, and each pixel circuit includes a driving transistor, a writing transistor, and a sensing transistor. The gate of the writing transistor is connected to the N-th scan line, and the gate of the sensing transistor is connected to the (N+1)-th scan line, allowing for shared gate driving circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two scan lines are used for each row of pixel circuits (one for data signal writing and one for potential detection), then the pixel circuit control function is improved, but the number of scan lines and gate driving circuits increases
Solution Approach 1:
The patent merges the function of the sensing transistor's gate control into the existing scan line structure. Specifically, the gate of the sensing transistor is connected to the same scan line that controls the writing transistor, allowing one scan line to serve dual purposes: controlling data writing and sensing operations sequentially. This eliminates the need for a separate dedicated sensing scan line for each pixel row.
Solution Approach 2:
The scan line is designed to perform multiple functions by controlling different transistors at different time periods. The same scan line controls both the writing transistor during the data writing phase and the sensing transistor during the sensing phase, making the scan line a multi-functional component that reduces overall circuit complexity.
2Manufacturing precision
If two different gate driving circuits are used to provide scan signals with different waveforms, then the scan signal control precision is improved, but the occupied space increases
Solution Approach 1:
The patent employs periodic action by controlling the writing transistor and sensing transistor at different time periods using the same scan line. During the first time period, the scan line controls the writing transistor for data writing; during the second time period, it controls the sensing transistor for sensing operations. This temporal separation allows precise control of different waveforms without requiring separate physical circuits.
Solution Approach 2:
The scan line dynamically switches between controlling different transistors based on the operational phase. The same physical scan line adapts its function over time, dynamically controlling the writing transistor when data writing is needed and the sensing transistor when sensing is needed, thereby eliminating the need for static separate circuits.
3Reliability
If two scan lines are used for each row of pixel circuits, then the pixel circuit control function is improved, but the border width increases
Solution Approach 1:
The patent merges the sensing control function into the existing scan line infrastructure. By connecting the sensing transistor gate to the same scan line that controls data writing, the design eliminates the need for additional dedicated sensing scan lines, thereby reducing the horizontal space required in the border region.
Solution Approach 2:
The scan line serves as a universal control line that performs both data writing and sensing functions. This multi-functionality reduces the number of separate control lines needed, directly contributing to narrower border width while maintaining complete pixel circuit control capability.
Data Source
AI summary
A display panel and a display device are provided. The display panel includes pixel circuits arranged in an array and scan lines. Each pixel circuit in a N-th row of pixel circuits includes a driving transistor, a writing transistor, and a sensing transistor. A N-th scan line is configured to control charging of the N-th row of pixel circuits, a (N+1)-th scan line is configured to control the charging of a (N+1)-th row of pixel circuits, a gate of the writing transistor in each pixel circuit of the N-th row of pixel circuits is electrically connected to the N-th scan line, and a gate of the sensing transistor in each pixel circuit of the N-th row of pixel circuits is electrically connected to the (N+1)-th scan line.