Display Panel Segmented Fanout Layout for Narrow Lower Borders

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Solution Overview

Problem

Current display technologies face challenges in achieving a 100% screen-to-body ratio due to limitations in reducing the size of the lower border of display panels, as the size of the lower border is often larger compared to the left and right borders, making it difficult to further minimize the width of the data line fanout area.

Innovation Solution

The implementation of a segmented fanout mode for data lines, where the data lines are distributed across multiple fanout sub-areas and power lines are used as intervals between these sub-areas, effectively reducing the width of the fanout area and thereby minimizing the lower border size, while maintaining the same resolution and design specifications.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If data lines are concentrated in a single fanout area, then wiring is simplified, but the lower border width increases

Engineering Contradiction:
Improvewiring complexityVSAvoidlower border width
Core Design Contradiction:
Device complexityVSLength of stationary object

Solution Approach 1:

The patent divides the fanout area into multiple fanout sub-areas (first fanout sub-area, second fanout sub-area, third fanout sub-area) and distributes different groups of data lines across these sub-areas. This segmentation reduces the concentration of wiring in any single location, thereby reducing the overall lower border width while maintaining organized wiring structure.

Inventive Principle:
Principle #1Segmentation

2Length of stationary object

If the lower border width is reduced, then screen-to-body ratio increases, but wiring space becomes insufficient

Engineering Contradiction:
Improvelower border widthVSAvoidwiring space
Core Design Contradiction:
Length of stationary objectVSArea of stationary object

Solution Approach 1:

The patent extends data lines not only in the horizontal direction but also in the vertical direction by utilizing multiple fanout sub-areas arranged in different dimensions. Data lines are distributed across first, second, and third fanout sub-areas located at different positions, effectively using two-dimensional space distribution to accommodate all wiring within a reduced overall border width.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Length of stationary object

If data lines are distributed across multiple fanout sub-areas, then lower border width is reduced, but device complexity increases

Engineering Contradiction:
Improvelower border widthVSAvoidfanout structure complexity
Core Design Contradiction:
Length of stationary objectVSDevice complexity

Solution Approach 1:

The patent combines multiple fanout sub-areas (first, second, and third fanout sub-areas) into a unified fanout structure that collectively accommodates all data lines. By merging these sub-areas with coordinated data line groups, the design achieves compact wiring distribution that reduces border width while maintaining manageable structural complexity through systematic organization.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS11837687B2Display panel and display apparatus
Publication Date: 2023.12.05 BOE TECHNOLOGY GROUP CO LTD
  • US11837687B2 patent drawing
  • US11837687B2 patent drawing
  • US11837687B2 patent drawing

AI summary

A display panel and a display apparatus are provided. The display panel includes an active area and a non-active area located at least on one side of the active area, wherein the non-active area includes a first fanout area; a plurality of sub-pixels located in the active area; a plurality of data lines located in the active area and extending from the active area to the first fanout area, the plurality of data lines electrically connected to the plurality of sub-pixels and configured to provide data signals for the plurality of sub-pixels; the first fanout area includes at least two data line fanout sub-areas, and the plurality of data lines are respectively located in the at least two data line fanout sub-areas.