Display Panel Pixel Circuits With Shared Scan-Line Layout
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Solution Overview
Problem
The layout design of pixel circuits in display panels affects circuit performance and display resolution, necessitating an optimization to improve pixel density and transmittance.
Innovation Solution
The anode reset transistor and data writing transistor of a pixel circuit are connected to the same scan line, allowing for a more compact layout and reduced signal voltage drop, with additional transistors and connections optimized to minimize space and enhance transmittance in transparent displays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the anode reset transistor and data writing transistor are connected to different scan lines, then the circuit layout has higher reliability and easier signal control, but the pixel circuit occupies more area and has lower pixel density
Solution Approach 1:
The patent merges the scan line connections by connecting both the anode reset transistor and data writing transistor to the same first scan line. This consolidation reduces the number of scan lines required and decreases the overall pixel circuit area, thereby improving pixel density while maintaining functional integrity through coordinated control signals.
Solution Approach 2:
The first scan line is designed to serve multiple functions by controlling both the anode reset transistor and data writing transistor. This multi-functionality approach allows a single scan line to perform what traditionally required separate dedicated lines, reducing area occupation and improving pixel density without compromising circuit reliability.
2Illumination intensity
If additional transistors and connections are added to optimize layout, then transmittance and pixel density improve, but signal voltage drop increases and circuit complexity increases
Solution Approach 1:
The patent optimizes the spatial arrangement of transistors and connections in the pixel circuit layout, utilizing efficient two-dimensional positioning to minimize signal path lengths. By strategically placing the anode reset transistor, data writing transistor, and their interconnections in a compact configuration, the design reduces the physical distance signals must travel, thereby minimizing voltage drop while maintaining improved transmittance and pixel density.
3Productivity
If the pixel circuit layout is optimized for higher pixel density, then transmittance improves, but the layout space reduction may compromise circuit performance
Solution Approach 1:
The patent applies local quality optimization by carefully designing the specific regions where transistors and connections are placed within the pixel circuit. The layout strategically positions the anode reset transistor and data writing transistor with optimized interconnections in high-density areas, ensuring that critical signal paths maintain adequate quality and performance characteristics even as overall pixel density increases.
Data Source
AI summary
Provided are a display panel and a display apparatus. The display panel comprises a substrate and pixel circuits on one side of the substrate. At least one of the pixel circuits comprises a driving transistor, a data writing transistor, and an anode reset transistor. The data writing transistor has a gate electrically connected to a first scan line, a first electrode electrically connected to a data line, and a second electrode electrically connected to a first electrode of the driving transistor. The anode reset transistor has a gate electrically connected to the first scan line, a first electrode electrically connected to a reset line, and a second electrode electrically connected to a light-emitting element. The anode reset transistor and the data writing transistor of a same pixel circuit are electrically connected to a same first scan line.