Display Panel Shield Line Reduces Capacitance Variations
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Solution Overview
Problem
Existing display panel interconnection structures face challenges in minimizing signal interference and maintaining uniform brightness across pixels due to variations in capacitance between common and clock signal lines, leading to potential horizontal lines on the display screen.
Innovation Solution
Incorporating a second line that receives a ground voltage and is electrically disconnected from stage circuits, and optionally a third floating line, between the common line and the gate driving circuit to shield the common line from clock signal lines, thereby reducing capacitance variations and maintaining uniform pixel brightness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the common line is disposed adjacent to the gate driving circuit without shielding, then the device complexity is reduced, but capacitance variations occur between the common line and clock signal lines causing non-uniform pixel brightness
Solution Approach 1:
A second line (shield line) is introduced as an intermediary element between the common line and the clock signal lines. This shield line is electrically disconnected from stage circuits and configured to reduce capacitance variations. By placing this intermediary shielding structure between the common line and clock signal lines, the patent prevents direct capacitive coupling that would cause brightness non-uniformity, while maintaining a relatively simple overall interconnection structure.
2Manufacturing precision
If shielding structures are added between the common line and clock signal lines, then capacitance variations are reduced and pixel brightness uniformity is improved, but the device complexity increases
Solution Approach 1:
The shield line serves as a minimal intermediary structure that effectively reduces capacitance variations without adding significant complexity. Rather than implementing complex multi-layer shielding or active compensation circuits, the patent uses a simple electrically-disconnected conductive line positioned between the common line and clock signal lines to achieve the desired effect.
Solution Approach 2:
The patent optimizes the electrical parameters of the shield line by configuring it to be electrically disconnected from stage circuits while maintaining its capacitive shielding function. This parameter change (electrical disconnection) allows the shield line to reduce capacitance variations between the common line and clock signal lines without introducing additional active circuitry that would increase device complexity.
3Adaptability or versatility
If the second line is electrically connected to stage circuits, then it can provide functional signals, but capacitance variations and signal interference occur affecting pixel brightness
Solution Approach 1:
The second line functions as a shielding intermediary rather than a signal-carrying conductor. By being electrically disconnected from stage circuits, it acts purely as a capacitive shield between the common line and clock signal lines, preventing signal interference while still providing the beneficial effect of reducing capacitance variations. This intermediary role resolves the conflict between functionality and interference prevention.
Solution Approach 2:
The patent extracts the shielding function from the second line by disconnecting it from stage circuits. Rather than attempting to make the line serve dual purposes (signal transmission and shielding), the design separates these functions: the clock signal lines carry signals, while the second line is extracted as a dedicated shielding element that is electrically isolated, thereby eliminating signal interference while maintaining capacitance reduction benefits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces capacitance variations between the common and clock signal lines, preventing horizontal lines and ensuring consistent pixel brightness by minimizing signal interference.
Implementation Method 1
a second line disposed between the first line and one of the clock signal lines which is disposed closest to the first line, and electrically disconnected from the stage circuits
Data Source
AI summary
A display device may include a first display substrate. The first display substrate may include a first line disposed in the non-display region to apply a common voltage to the display region, a gate driving circuit disposed in the non-display region between the display region and the first line, gate lines connected to the gate driving circuit, and a second line disposed between the first line and the gate driving circuit. The gate driving circuit may include clock signal lines, each of which receives a clock signal, and stage circuits connected to corresponding ones of the clock signal lines and the gate lines to output gate signals. The second line may be disposed between the first line and one of the clock signal lines disposed closest to the first line and may be electrically disconnected from the stage circuits.