Display Panel Pixel Circuit Shielding for Crosstalk Reduction
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Solution Overview
Problem
Current display panels face challenges in achieving high-resolution and high-quality image display due to limitations in the design of pixel circuits, particularly in minimizing parasitic capacitance and crosstalk between signal lines, which affect image clarity and integration density.
Innovation Solution
The display panel incorporates a substrate with specific arrangements of thin film transistors, including a silicon semiconductor and an oxide semiconductor, along with a shield line and node connection line configurations that reduce parasitic capacitance and crosstalk, such as isolated upper gate electrodes and double gate structures, to enhance image quality and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional pixel circuit designs are used, then manufacturing is simpler, but parasitic capacitance and crosstalk increase, reducing image quality
Solution Approach 1:
A shield line is introduced as an intermediary conductive element positioned between the data line and node connection line. This shield line acts as a mediator to block electromagnetic interference and reduce parasitic capacitance between adjacent signal lines, thereby improving image quality without fundamentally changing the pixel circuit architecture
Solution Approach 2:
The shield line is positioned in a vertical dimension between existing planar signal lines (data line and node connection line). By utilizing the vertical space above the substrate, the design reduces parasitic capacitance without increasing the horizontal footprint of the pixel circuit, thus maintaining integration density while improving image quality
2Productivity
If signal lines are placed closer together to increase integration density, then productivity improves, but crosstalk and parasitic capacitance increase, worsening image clarity
Solution Approach 1:
The shield line serves as a protective intermediary that enables closer spacing of signal lines by blocking electromagnetic coupling between them. This allows the data line and node connection line to be positioned nearer to each other for higher integration density, while the shield line prevents crosstalk that would otherwise degrade image clarity
Solution Approach 2:
The conductive shield line is segmented into discrete portions positioned at critical locations where parasitic capacitance has the greatest impact. This segmentation approach provides effective shielding against crosstalk while minimizing the total amount of additional conductive material required, thus supporting high integration density without compromising image clarity
Data Source
AI summary
A display panel includes a substrate, a first thin film transistor including a first semiconductor layer and a first gate electrode, a data line extending in a first direction, a scan line extending in a second direction, a second thin film transistor electrically connected to the data line and including a second semiconductor layer and a second gate electrode, a third thin film transistor including a third semiconductor layer and a first upper gate electrode arranged on the third semiconductor layer, a node connection line electrically connecting the first thin film transistor and the third thin film transistor, and a shield line located between the data line and the node connection line in a plan view and including the same material as the first upper gate electrode of the third thin film transistor. The first semiconductor layer includes a silicon semiconductor, and the third semiconductor layer includes an oxide semiconductor.