Display Panel Shift Register Drive Circuit Adaptability
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Solution Overview
Problem
Conventional display panels cannot meet diversified display requirements due to identical drive modes for pixel rows, limiting their application scenarios and flexibility in refresh rates.
Innovation Solution
A display panel with a drive circuit featuring cascaded shift registers, where each stage includes a control unit, an initial output unit, and a first output unit, allowing independent control of signal polarity and frequency for each row, enabling flexible drive modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If identical drive modes are used for all pixel rows, then the drive circuit structure is simple, but the display panel cannot meet diversified display requirements
Solution Approach 1:
The drive circuit is segmented into multiple independent shift register stages (first stage, second stage, etc.), where each stage can be independently controlled. The control unit can selectively activate different stages to drive different pixel rows, enabling diversified display modes without requiring a completely different circuit architecture for each mode.
Solution Approach 2:
The drive circuit incorporates dynamic switching capabilities through the control unit, which can adjust the operating mode of shift register stages based on display requirements. The circuit can dynamically transition between single-stage mode, multi-stage mode, and different refresh rate configurations, making the system adaptable to various display scenarios.
2Adaptability or versatility
If cascaded shift registers with independent control are used, then diversified display requirements can be met, but the drive circuit structure becomes more complex
Solution Approach 1:
Each shift register stage is designed as a universal module that can function in multiple capacities. The same basic shift register structure can operate in different stages of the cascade, with each stage capable of driving pixel rows at different refresh rates. This modular universality reduces overall complexity compared to designing specialized circuits for each function.
Solution Approach 2:
The control unit changes operational parameters (such as clock signal frequency, enable signals, and output selection) to achieve different display modes without changing the fundamental circuit structure. By adjusting parameters like the refresh rate of different pixel rows and the polarity of drive signals, the system achieves versatility while maintaining a consistent hardware architecture.
3Adaptability or versatility
If all pixel rows are refreshed at the same rate, then the drive circuit is simple to control, but the display panel cannot achieve different refresh rates for different rows
Solution Approach 1:
Different pixel rows can have different refresh rates assigned to them through the cascaded shift register structure. The control unit applies local quality control by enabling specific stages to operate at different frequencies based on the display requirements of corresponding pixel rows, allowing high refresh rates in certain regions while maintaining lower rates in others.
Solution Approach 2:
The control unit implements periodic action by applying clock signals with different frequencies to different shift register stages. This allows certain pixel rows to be refreshed at higher periodic intervals while others use lower intervals, optimizing power consumption and display performance for different regions of the display panel.
Data Source
AI summary
Provided are a display panel and a display device. The display panel includes a drive circuit including cascaded N stage shift registers. A shift register includes a control unit, an initial output unit and a first output unit. The control unit is configured to at least receive an input signal and control a signal of the first output node and a signal of the second output node. The initial output unit is configured to at least receive a signal of the first output node and a signal of the second output node, and control an initial output signal; the initial output signal of an xth stage shift register is the input signal of a yth stage shift register. The first output unit is configured to at least receive the signal of the first output node and the signal of the second output node, and control a first output signal.