Display Panel Shot Overlap Pattern Matching
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Solution Overview
Problem
The increasing size and resolution of display panels lead to pattern mismatches during the divided exposure process, resulting in defects like stitch lines and increased manufacturing time and costs due to the need for more shots and smaller driver ICs.
Innovation Solution
A display panel design that includes dummy pads and a manufacturing method using a divided exposure process with overlapping portions, where the patterns of overlapping shots are accurately matched using double exposure units, reducing the number of shots and preventing pattern mismatches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the display panel size and resolution are increased, then the display quality is improved, but the number of shots required for divided exposure increases causing more pattern mismatches and stitch defects
Solution Approach 1:
The patent applies preliminary action by forming a shot overlapping portion with a predetermined width before the final pattern formation. This overlapping region is prepared in advance to accommodate pattern matching between adjacent shots, preventing stitch defects and pattern mismatches that would otherwise occur at shot boundaries during high-resolution divided exposure processes
2Manufacturing precision
If the shot overlapping portion width is increased to prevent pattern mismatches, then pattern accuracy is improved, but the number of driver ICs in the overlapping portion increases causing processing losses
Solution Approach 1:
The patent applies local quality by differentiating the treatment of overlapping portions from the rest of the substrate. The shot overlapping portion with predetermined width is given special attention for pattern matching, while other regions follow standard exposure procedures. This localized approach ensures pattern accuracy at critical boundaries without unnecessarily increasing processing time across the entire panel
3Manufacturing precision
If the number of pixels is increased for high resolution, then display quality is improved, but the number of driver ICs increases causing more complex exposure processes
Solution Approach 1:
The patent applies segmentation by dividing the exposure process into multiple shots with a predetermined shot overlapping portion. This segmentation strategy allows the complex high-resolution pattern to be formed through multiple manageable exposure steps, with the overlapping region serving as a buffer that simplifies the coordination between shots and reduces the complexity impact of having numerous driver ICs
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing time and costs by minimizing pattern mismatches and stitch defects, allowing for efficient production of high-resolution display panels with fewer shots and maintaining pattern accuracy.
Implementation Method 1
a photoresist pattern forming process through selective exposure and development of a photoresist using a mask
Data Source
AI summary
A display panel including: a display portion including a plurality of signal lines and a plurality of pixels connected to the signal lines; a peripheral portion provided around the display portion; an integrated circuit (IC) mounting unit provided on the peripheral portion, and including a plurality of driver ICs connected to a data driver; and a test pad portion provided on the peripheral portion and testing the signal lines. The test pad portion includes a gate driver test pad portion including a gate driver test pad unit and a data line test pad unit including a data line test pad unit, the data line test pad unit includes an outermost data line test pad unit provided on respective sides of the data line test pad portion and a plurality of intermediate data line test pad units provided between the outermost data line test pad units.


