Display Panel Signal Calibration for RC Delay Compensation
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Solution Overview
Problem
In display panels, the resistor-capacitor delay causes distortion in gate and data signal waveforms, leading to incorrect pixel charging and calibration challenges due to the proximity of signal circuits to the panel display area.
Innovation Solution
The display panel design includes a signal generating circuit, pixel array, and gate driver circuits, where the signal generating circuit provides clock and data signals, and the gate driver circuits convert these signals. The circuit configuration calibrates the signals by adjusting their delays along opposite directions, using bus lines with varying lengths and U-shaped portions to minimize distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the signal generating circuit and gate driver circuits are located close to the panel display area, then the device complexity is reduced and integration is improved, but the gate and data signals experience severe waveform distortion due to resistor-capacitor delay
Solution Approach 1:
The patent applies preliminary action by introducing delay compensation mechanisms before the distorted signals reach the pixel array. The signal generating circuit pre-adjusts the timing of gate and data signals to counteract the expected RC delay, ensuring that signals arrive at the pixel array with correct timing relationships despite the proximity-induced delays.
Solution Approach 2:
The patent changes signal timing parameters dynamically. Different gate signals and data signals are assigned different delay compensation values based on their transmission distances. The signal generating circuit adjusts phase and timing parameters of individual signals to compensate for position-dependent RC delays, transforming the uniform timing approach into a customized timing scheme.
2Use of energy by moving object
If the gate driver circuits are positioned to minimize routing distance, then the use of energy is reduced and signal transmission efficiency is improved, but calibration becomes more difficult due to varying delays across different positions
Solution Approach 1:
The patent applies local quality by implementing position-specific delay compensation for each gate driver circuit. Instead of using a uniform calibration approach, the signal generating circuit provides customized timing adjustments tailored to the specific transmission characteristics of each position. This localized calibration strategy simplifies the overall process by addressing each position's unique delay profile rather than attempting a global solution.
Solution Approach 2:
The signal generating circuit performs self-calibration by automatically measuring and compensating for RC delays at each position. The system uses built-in test functions to characterize the delay of each gate and data signal path, then automatically adjusts timing parameters without requiring external calibration equipment or complex manual adjustment procedures.
3Area of stationary object
If bus lines are extended to reach distant pixels, then the coverage area is increased, but the resistor-capacitor delay increases causing severe waveform distortion
Solution Approach 1:
For extended bus lines reaching distant pixels, the patent applies preliminary action by pre-compensating for the increased RC delay in the timing generation stage. The signal generating circuit calculates the expected delay based on bus line length and signal characteristics, then advances the timing of signals destined for distant pixels before transmission, ensuring synchronized arrival at pixels regardless of distance.
Solution Approach 2:
The patent dynamically changes timing parameters based on pixel position and bus line characteristics. Signals destined for distant pixels receive greater delay compensation than those for nearby pixels. The system adjusts phase, frequency, and timing parameters according to the specific transmission path length, transforming a fixed timing system into an adaptive one that maintains accuracy across extended coverage areas.
Data Source
AI summary
A display panel includes a signal generating circuit, a pixel array disposed adjacent to the signal generating circuit, and a plurality of gate driver circuits disposed adjacent to the signal generating circuit and the pixel array. The signal generating circuit is configured to provide a plurality of clock signals and a plurality of data signals. The gate driver circuits are configured to convert the clock signals to a plurality of gate signals and transfer the gate signals to the pixel array. The pixel array is configured to receive the gate signals and the data signals for display. Delays of the gate signals increase along a first direction, delays of the data signals increase along a second direction, and the second direction is opposite to the first direction. The signal generating circuit is further configured to calibrate the gate signals and the data signals.