Display Panel Pixel Circuit Signal Line Merging
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Solution Overview
Problem
Existing display panels have a large number of signal lines in the pixel circuit, limiting the reduction of layout size and area, which affects the resolution and transmittance of the display.
Innovation Solution
The pixel circuit design incorporates a data write module, drive module, and reset module, where the first signal line functions as both the data signal line and reference voltage line, eliminating the need for a separate reference voltage line, thereby reducing the number of signal lines and minimizing the layout size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate reference voltage line is disposed in the display panel, then the pixel circuit can function properly with stable voltage reference, but the number of signal lines increases and the layout size of the pixel circuit cannot be reduced
Solution Approach 1:
The patent merges the reference voltage line function with the data signal line by connecting both the data write module and the reset module to the same first signal line. This allows the first signal line to serve dual purposes: transmitting data signals to the data write module and providing reference voltage to the reset module, thereby eliminating the need for a separate reference voltage line and reducing the pixel circuit layout area
Solution Approach 2:
The first signal line is designed to perform multiple functions simultaneously: it acts as both a data signal line for the data write module and a reference voltage line for the reset module. This multi-functionality approach reduces the total number of signal lines required in the pixel circuit while maintaining proper circuit operation and stability
2Area of stationary object
If the number of signal lines in the pixel circuit is reduced, then the layout size can be reduced and resolution improved, but the circuit design becomes more complex with shared signal lines
Solution Approach 1:
The patent segments the timing of signal transmission by dividing the frame period into distinct phases: a reset phase where the first signal line provides reference voltage to the reset module, and a data writing phase where the same line transmits data signals to the data write module. This temporal segmentation allows the shared signal line to serve multiple functions without interference, reducing layout complexity while maintaining circuit functionality
Data Source
AI summary
Provided are a display panel and a display device. The display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a data write module, a drive module and a first reset module. The data write module is configured to transmit a data signal in response to a scan signal of a first scan terminal. The drive module is configured to provide a drive current for the light-emitting element and includes a drive transistor. The drive transistor is configured to generate the drive current according to the data signal. The first reset module is connected between a first signal line and a gate of the drive transistor and configured to transmit a signal of the first signal line to the gate of the drive transistor. The data write module is connected between the first signal line and an input terminal of the drive transistor.