Display Panel Signal Multiplexing Reduces IC Count
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Solution Overview
Problem
Conventional display panels require multiple driving integrated circuits (ICs) and flexible printed circuit (FPC) boards as data lines increase, leading to increased fabrication time due to the complexity of bonding these components.
Innovation Solution
The display panel design incorporates a first switching element coupled to a data line and a storage capacitor, allowing data to be stored and transferred efficiently using fewer signal lines, reducing the number of driving ICs and FPC boards needed by enabling two signal lines to drive three data lines through signal control circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple data lines are used to increase display resolution, then display quality is improved, but the number of driving ICs and FPC boards increases leading to longer fabrication time
Solution Approach 1:
The patent implements a multi-functional signal line system where two signal lines (first and second signal lines) are used to drive three data lines (first, second, and third data lines) through time-division multiplexing. The signal lines alternately connect to different data lines during different time periods, allowing a reduced number of signal lines to control more data lines than traditionally required, thereby reducing the number of driving ICs and FPC boards needed while maintaining high display resolution
Solution Approach 2:
The patent employs dynamic switching elements (first and second switching elements) that change their connectivity state between different time periods. During a first time period, the switching elements connect the first signal line to the first data line and the second signal line to the second data line. During a second time period, they reconfigure to connect the first signal line to the third data line and the second signal line to the second data line. This dynamic reconfiguration allows the same physical signal lines to serve multiple data lines sequentially, reducing the total number of permanent connections required
2Productivity
If the number of driving ICs is increased to support more data lines, then data transfer capability is improved, but device complexity and fabrication complexity increase
Solution Approach 1:
The patent makes the first and second signal lines universal by enabling them to drive multiple different data lines at different time periods through the switching elements. Instead of requiring dedicated signal lines for each data line (which would necessitate multiple driving ICs), the same signal lines are reused across different time periods to control the first, second, and third data lines, thereby reducing the number of driving ICs and FPC boards required while maintaining full data transfer capability to all data lines
3Reliability
If more FPC boards are used to connect driving ICs to data lines, then connectivity is improved, but bonding time and fabrication time increase
Solution Approach 1:
The patent merges the functionality of multiple signal lines into fewer physical signal lines by using time-division multiplexing. Instead of requiring separate FPC boards for each driving IC connection, the system consolidates the signal paths so that two signal lines can serve three data lines through sequential switching. This merging reduces the total number of FPC boards required and consequently reduces the bonding time and fabrication complexity associated with connecting multiple FPC boards to multiple driving ICs
Data Source
AI summary
Display panels buffering display data from a data driver. The display panel comprises a first signal line, a first data line, a first scan line interlaced with the first data line, a first pixel coupled to the first data line and the first scan line, a first switching element comprising a first terminal coupled to the first data line, a first storage capacitor coupled between a second terminal of the first switching element and a ground, and a second switching element coupled to the first storage capacitor and the first signal line.