Display Panel Signal Timing and Connection-Wire Segmentation
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Solution Overview
Problem
The coupling between signal lines in display panels, particularly between scan lines and connection wires, leads to abnormal data signals, affecting the display effect.
Innovation Solution
The display panel design separates signal write control lines and reset control lines, ensuring that the enable levels of these lines do not overlap, and the voltage edges of the reset control signals are timed to avoid interfering with data signal writing, using a novel timing scheme to reduce coupling effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If connection wires are provided in the display region to connect data lines to fan-out wires, then the bezel can be made narrow, but coupling between signal lines occurs causing abnormal data signals
Solution Approach 1:
The connection wire is divided into two separate segments: a first connection wire segment extending along the first direction and a second connection wire segment extending along the second direction. This segmentation reduces the coupling effect between the connection wire and scan lines by breaking the continuous path into orthogonal segments, thereby eliminating abnormal data signals while maintaining the narrow bezel design.
2Reliability
If reset control signals are applied to pixel circuits, then pixel circuits can be reset properly, but the enable levels of reset control signals may overlap with data signal writing causing interference
Solution Approach 1:
The reset control signal is timed to be applied before the data signal writing operation. Specifically, the enable level of the reset control signal is configured to occur prior to the enable level of the write control signal, ensuring that pixel circuits are fully reset before data writing begins. This preliminary action prevents any potential interference between reset and data writing operations.
Solution Approach 2:
The control signals are applied in a periodic sequence where reset operations and data writing operations are separated in time. The timing scheme ensures that the enable levels of reset control signals do not overlap with the enable levels of write control signals, creating a periodic pattern of reset-then-write operations that eliminates signal interference.
Data Source
AI summary
A display panel includes a plurality of pixel circuits, a plurality of signal write control lines, a plurality of reset control lines, a plurality of data lines, and a plurality of connection wires; the connection wire includes a first connection wire segment and a second connection wire segment; and a reset control signal provided for the (N+i+1)-th row of pixel circuits is an (N+i+1)-th reset control signal, and a write control signal provided for the N-th row of pixel circuits is an N-th write control signal, where a first voltage edge and/or a second voltage edge of an enable level of the (N+i+1)-th reset control signal do not overlap an enable level of the N-th write control signal; and in an enable level of the same reset control signal, the second voltage edge is after the first voltage edge, N is a positive integer, and i is a natural number.