Display Panel Data Line Reduction via Signal Trace Merging

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Solution Overview

Problem

Conventional LCD panel manufacturing costs are high due to the complexity and cost of source driving structures, particularly in one third source driving (OTSD) structures, which require significant reduction in data lines and manufacturing adjustments.

Innovation Solution

A display panel design that reduces the number of data lines by one third, utilizing a combination of data lines, gate signal traces, and optionally floated metal wires or common voltage lines to transmit signals and voltages, allowing for a slim border and simplified manufacturing processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If the number of data lines is reduced to implement one third source driving (OTSD) structure, then manufacturing cost is reduced, but device complexity and manufacturing difficulty increase

Engineering Contradiction:
Improvemanufacturing costVSAvoiddata line configuration complexity
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent combines gate signal traces with data line functions, allowing the same trace to carry both gate signals and data signals at different times. This merging approach reduces the total number of data lines required while maintaining full functionality, directly addressing the cost reduction goal without proportionally increasing complexity

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent implements dynamic signal routing where data lines can be dynamically assigned to different pixel columns in different time periods. This dynamic allocation allows fewer physical data lines to serve more pixel columns, achieving the one third source driving structure while managing complexity through time-multiplexed operation

Inventive Principle:
Principle #15Dynamics

2Ease of manufacture

If the number of data lines is reduced by one third, then manufacturing cost decreases, but signal transmission reliability may deteriorate

Engineering Contradiction:
Improvemanufacturing costVSAvoidsignal transmission reliability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent employs periodic scanning where data signals are transmitted in sequential time periods to different pixel columns. Each data line serves multiple columns through time-multiplexed periodic operation, reducing the number of simultaneous connections needed while ensuring reliable signal delivery to all pixels through systematic sequential addressing

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent introduces signal traces as intermediary elements that bridge the reduced set of data lines to the expanded set of pixel columns. These traces act as intermediate transmission paths that enable reliable signal distribution across more pixels than the number of physical data lines would traditionally support

Inventive Principle:
Principle #24Intermediary (Mediator)

3Shape

If data lines and signal traces are disposed between pixel columns, then pixel spacing is maintained, but manufacturing precision requirements increase

Engineering Contradiction:
Improvepixel spacingVSAvoidtrace positioning precision
Core Design Contradiction:
ShapeVSManufacturing precision

Solution Approach 1:

The patent segments the display area into distinct regions with data lines and signal traces positioned in the spaces between pixel columns. This segmentation allows the signal transmission elements to be placed in dedicated inter-column regions, maintaining pixel spacing while creating defined manufacturing zones that reduce precision requirements compared to placing traces within pixel areas

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS9423660B2Display panel
Publication Date: 2016.08.23 AU OPTRONICS CORP
  • US9423660B2 patent drawing
  • US9423660B2 patent drawing
  • US9423660B2 patent drawing

AI summary

A display panel is provided. The display panel has a display area and a peripheral area and includes a plurality of pixels, a plurality of data lines and a plurality of signal traces. The pixels are disposed on the display area and arranged in an array. The data lines extend from the display area to the peripheral area and are respectively electrically connected to a plurality of columns of pixel. The signal traces extend from the display area to the peripheral area and are parallel to the data lines. In addition, the data lines and the signal traces are respectively disposed between two columns of pixels, and the signal traces include a plurality of gate signal traces.