Display Panel Layout With Stacked Drain Electrodes for Higher Resolution
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Solution Overview
Problem
Current display panels face limitations in increasing resolution due to constraints in layout space and process capabilities, particularly with liquid crystal display panels, which restrict further improvement.
Innovation Solution
The display panel design includes a substrate with a first metal layer containing data lines and thin-film transistors, where the drain electrode is located between adjacent data lines in a separate second metal layer, allowing for reduced parasitic capacitance and closer data line spacing, thereby enabling smaller sub-pixel sizes and improved resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the resolution of display panels is increased, then the pixel density is improved, but the layout space and process capabilities are exceeded
Solution Approach 1:
The patent applies three-dimensional stacking by placing the drain electrode in a second metal layer above the first metal layer containing data lines. This vertical arrangement allows the drain electrode to be positioned between adjacent data lines without requiring additional horizontal space, thereby enabling higher resolution while maintaining the same layout area.
Solution Approach 2:
The patent nests the drain electrode within the space between adjacent data lines by utilizing the vertical dimension. The drain electrode is positioned in the second metal layer directly above the region between two data lines in the first metal layer, effectively nesting components within the existing layout footprint to achieve higher pixel density.
2Length of moving object
If the distance between data lines and drain electrodes is reduced, then the sub-pixel size is reduced, but parasitic capacitance increases
Solution Approach 1:
The patent reduces parasitic capacitance by transitioning from a planar arrangement to a three-dimensional arrangement. By positioning the drain electrode in the second metal layer above the first metal layer, the vertical separation increases the distance between the data line and drain electrode, thereby reducing capacitive coupling while still allowing compact sub-pixel dimensions.
Data Source
AI summary
A display panel and a display terminal are provided. The display panel includes a substrate, a first metal layer disposed on the substrate, and a second metal layer disposed above the first metal layer. The first metal layer includes a plurality of data lines extending in a first direction and thin-film transistors each including a source electrode. The source electrode is electrically connected to a corresponding one of the data lines. The second metal layer includes a drain electrode of the thin-film transistor, and the drain electrode is located between adjacent ones of the data lines.