Display Panel Stacked Gate Electrode Voltage Reduction

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing display panels require high data signal voltage to display a black frame, leading to high power consumption.

Innovation Solution

A display panel design that includes a pixel driving circuit with specific transistor configurations and conductive layers, allowing for reduced data signal voltage requirements by optimizing the gate electrode configurations and parasitic capacitance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by stationary object

If conventional display panel design is used, then black frame display is achieved, but power consumption is high

Engineering Contradiction:
Improvepower consumptionVSAvoiddata signal voltage
Core Design Contradiction:
Use of energy by stationary objectVSUse of energy by moving object

Solution Approach 1:

The patent introduces a new spatial dimension by adding a second gate electrode (G2) stacked vertically above the first gate electrode (G1) for the same transistor. This three-dimensional gate structure increases the effective gate area without expanding the planar footprint, thereby enhancing control over the channel and reducing the voltage required for black frame display, which directly addresses the high power consumption issue.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent merges multiple functions into the stacked gate structure. The first gate electrode (G1) and second gate electrode (G2) work together to control the same transistor channel, creating a combined gating effect that improves electron control and reduces leakage current. This merging of control functions allows for lower operating voltage while maintaining display performance.

Inventive Principle:
Principle #5Merging (Combining)

2Use of energy by stationary object

If data signal voltage is reduced, then power consumption decreases, but display performance may be compromised

Engineering Contradiction:
Improvepower consumptionVSAvoiddisplay performance
Core Design Contradiction:
Use of energy by stationary objectVSReliability

Solution Approach 1:

By stacking the second gate electrode above the first gate electrode, the patent creates additional control surface area in the vertical dimension. This enhanced gate control compensates for the reduced voltage by improving the electric field effectiveness, ensuring that display performance (contrast ratio, response time) is maintained even at lower operating voltages.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent changes the structural parameter of the gate electrode from a single-layer to a multi-layer stacked configuration. This structural parameter change increases the gate capacitance and control efficiency, allowing the system to operate at lower voltages while maintaining the necessary electrical characteristics for reliable display performance.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution enables efficient black frame display with lower data signal voltage, thereby reducing power consumption and improving display performance.

Implementation Method 1

a third conductive part provided in a different conductive layer from the second conductive layer, an orthographic projection, on the base substrate, of the third conductive part being at least partially overlapped with an orthographic projection, on the base substrate, of the second conductive part

Methodology Applied
Scientific EffectParasitic capacitance: Parasitic Capacitance

Data Source

PatentUS20250143113A1Display panel and display device
Publication Date: 2025.05.01 CHENGDU BOE OPTOELECTRONICS TECH CO LTD
  • US20250143113A1 patent drawing
  • US20250143113A1 patent drawing
  • US20250143113A1 patent drawing

AI summary

A display panel including a pixel driving circuit having driving transistor and fourth transistor is provided. The fourth transistor includes a first electrode connected to a data line and a second electrode connected to a first electrode of the driving transistor. The display panel includes: a first conductive layer provided on a base substrate and including a gate line and first conductive part, a portion of the gate line forming a gate electrode of the fourth transistor, the first conductive part forming a gate electrode of the driving transistor; a second conductive part connected to the gate line; a third conductive part provided in a different layer from the second conductive part, an orthographic projection of the third conductive part on the base substrate being partially overlapped with that of the second conductive part; a first bridging part connected to the third conductive part and the first conductive part.