Stacked Conductive Layers Reduce Frame Area in Display Panels
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Solution Overview
Problem
As display panels with increasing size and resolution require more pixel electrodes, the number of connecting wires increases, leading to a wider frame region that cannot be reduced effectively, limiting the size of the display area.
Innovation Solution
The array substrate includes a frame region with a reduced size by using a wire region with first and second conductive layers stacked and electrically connected through a via, allowing for thinner and more efficient signal transmission wires, and multiple signal wire layers that are electrically insulated and partially overlapped, reducing the wire width and frame area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of pixel electrodes is increased to improve display resolution, then the display quality is improved, but the number of connecting wires increases leading to a wider frame region
Solution Approach 1:
The patent transitions from planar wire arrangement to three-dimensional stacked conductive layers. Multiple conductive layers are arranged vertically with vias connecting corresponding positions, enabling wires to be organized in the thickness direction rather than only in the plane, thereby reducing frame region width
Solution Approach 2:
The patent implements nested conductive layers where multiple wire layers are stacked within the frame region. The first, second, and third conductive layers are positioned at different heights and connected through vias, creating a nested structure that accommodates more wires in a compact vertical space
2Adaptability or versatility
If more wires are added to connect increased pixel electrodes, then the connectivity is improved, but the wire width and frame area increase
Solution Approach 1:
The patent utilizes the thickness direction to arrange multiple conductive layers vertically. This dimensional transition allows wires to be stacked rather than spread out in the plane, maintaining high connectivity while reducing the horizontal frame area
Solution Approach 2:
The patent divides the wire structure into multiple segmented conductive layers. Each layer contains specific wires that are electrically connected through vias, creating a segmented yet integrated wiring system that improves connectivity efficiency
Data Source
AI summary
The present application provides a display panel. The display panel includes an array substrate which includes a display region and a frame region. The frame region includes a gate circuit drive unit, the gate circuit drive unit comprises a thin film transistor, and the thin film transistor comprises a source, a drain and a gate. The frame region further includes a driving circuit and a first signal lead line, the first signal lead line is arranged on a single layer and arranged on a same layer as the signal transmission wire layer, one end of the first signal lead line is electrically connected to the gate and the other end of the first signal lead line is electrically connected to the driving circuit.