Display Panel Storage Capacitor Design via Vertical Electrode Stacking
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Solution Overview
Problem
The challenge is to increase the storage capacitor capacity in a display panel without compromising the limited layout space, while maintaining the operating electrical properties of other elements.
Innovation Solution
The solution involves a display panel design where a first common electrode is electrically coupled with the capacitor electrode to form a first storage capacitor, and a second common electrode is electrically coupled with the pixel electrode to form a second storage capacitor. The second common electrode has a larger overlapping area with the pixel electrode compared to the first common electrode and the capacitor electrode, resulting in a higher capacitance value for the second storage capacitor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Illumination intensity
If the pixel structure size is reduced to achieve better display quality, then the display quality is improved, but the layout space of the storage capacitor is compressed
Solution Approach 1:
The patent utilizes the vertical dimension by stacking multiple common electrodes (first common electrode, second common electrode, third common electrode) at different heights above the capacitor electrode. This three-dimensional arrangement increases the overlapping area between electrodes without expanding the horizontal footprint, thereby increasing storage capacitance while maintaining compact pixel structure size.
Solution Approach 2:
The patent employs a nested configuration where multiple common electrodes are positioned at different vertical levels, creating a layered structure. The first common electrode is closest to the capacitor electrode, followed by the second common electrode, and then the third common electrode further away. This nested arrangement maximizes the use of vertical space to increase capacitance within the limited horizontal area.
2Quantity of substance
If multiple storage capacitors are integrated to increase total capacitance, then the storage capacitor capacity is improved, but the process integration complexity increases
Solution Approach 1:
The patent combines multiple storage capacitor functions into a single integrated structure. Instead of implementing separate capacitors that would require multiple fabrication processes, the design merges the function of multiple capacitors by stacking multiple common electrodes over a single capacitor electrode, all formed through an integrated process flow. This reduces process complexity while achieving the desired total capacitance.
Solution Approach 2:
The capacitor electrode serves multiple functions simultaneously by interacting with multiple common electrodes at different vertical levels. This single capacitor electrode structure performs the role of multiple capacitors, eliminating the need for separate capacitor structures and simplifying the overall fabrication process while maintaining high storage capacitance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively increases the overall storage capacitor capacity of the pixel structure by enhancing the overlapping area and capacitance value of the second storage capacitor, while maintaining the operational integrity of other elements.
Implementation Method 1
the first common electrode is electrically coupled to the capacitor electrode to form a first storage capacitor, and the second common electrode is electrically coupled to the pixel electrode to form a second storage capacitor
Data Source
AI summary
A display panel includes a substrate, multiple scan lines, multiple data lines, and multiple pixel structures. The scan lines and the data lines are disposed on the substrate. The pixel structure is disposed on the substrate and electrically connected to the scan lines and the data lines, and includes an active device, a pixel electrode, a capacitor electrode, an overcoat layer, a first common electrode, a second common electrode, a first passivation layer, and a second passivation layer. The active device is electrically connected one scan line, one data line, and the pixel electrode. The capacitor electrode extends from a drain and is electrically connected to the pixel electrode. The overcoat layer is disposed between the pixel electrode and the capacitor electrode. The first common electrode overlaps the capacitor electrode, and is located between the overcoat layer and the capacitor electrode. The second common electrode overlaps the pixel electrode, and is located between the overcoat layer and the pixel electrode. The first passivation layer is disposed between the capacitor electrode and the first common electrode. The second passivation layer is disposed between the second common electrode and the pixel electrode.