Display Panel Subregion Switching for High-Resolution 3D Display
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current 3D display technologies face challenges in achieving high resolution while managing system bandwidth and cost, as higher resolutions require greater data processing capacity and increased system demands.
Innovation Solution
The display panel incorporates a base substrate with sub-pixels, data lines, and gate lines, featuring a selection signal line group that allows for independent control of display subregions, minimizing the impact on sub-pixel aperture ratio and enabling partition display.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high-resolution display is implemented for 3D display, then display quality is improved, but system bandwidth and data processing capacity requirements increase leading to higher costs
Solution Approach 1:
The display panel is divided into multiple independent display subregions (first display subregion, second display subregion, etc.) that can be independently controlled. Each subregion corresponds to a specific selection signal line group, allowing selective activation of different regions based on user needs, thus reducing the overall data processing burden while maintaining high resolution in active areas
Solution Approach 2:
Different display subregions can be configured with different resolutions or quality levels. The pixel circuits in different subregions can have different characteristics, allowing high-resolution display in critical areas while using lower resolution in less critical areas, optimizing the balance between display quality and system complexity
2Adaptability or versatility
If thin film transistors are added for partition control, then partition display capability is improved, but aperture ratio decreases
Solution Approach 1:
The selection signal lines are merged with the gate line structure. The selection signal lines overlap with the gate lines in the vertical direction and share the same routing path in the horizontal direction. This integration allows the transistor to be controlled by both the gate line and selection signal line without requiring additional separate control transistors, thereby maintaining aperture ratio while achieving partition control capability
Solution Approach 2:
The gate lines serve dual functions: they act as both the gate electrode for the transistor and as routing paths for the selection signal lines. This multi-functionality reduces the need for additional dedicated control structures, preserving the aperture ratio while enabling region selection capability
3Adaptability or versatility
If selection signal lines overlap with active semiconductor layer, then partition display is achieved, but transistor control complexity increases
Solution Approach 1:
The transistor control mechanism is made dynamic and conditional. The transistor can be turned on by either the gate line alone or the selection signal line alone or both simultaneously, depending on the display mode requirements. This dynamic control flexibility allows the same hardware structure to support both full-display mode and partitioned display mode without increasing structural complexity
Data Source
AI summary
A display panel and a display device are provided. The display panel includes sub-pixels, data lines and gate lines. The sub-pixels include pixel circuits connected to the data lines and the gate lines. The display panel includes display subregions and selection signal line groups in one-to-one correspondence, each display subregion includes at least two sub-pixels, each selection signal line group includes selection signal lines, and the selection signal lines corresponding to different display subregions are insulated from each other; the pixel circuit includes a transistor in which an active semiconductor layer includes a first part and a second part, the first part overlaps with the gate line electrically connected with the transistor, and the second part overlaps with at least one selection signal line, and the gate line and the selection signal line are both configured to turn on the transistor upon being input with a turn-on voltage.