Display Panel Bonding Layout to Shield OLED Cell Test Pins
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In OLED display screens, the arrangement of cell test pins in chamfered Dummy regions leads to exposure and potential short circuits after laser cutting, causing display issues during verification.
Innovation Solution
The display panel design includes cell test pins arranged in the bonding region, with a chip on film that completely covers these pins, preventing exposure and using an anisotropic conductive film for shielding and electrical connection, thereby avoiding short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If cell test pins are arranged in chamfered Dummy regions, then the display screen can be manufactured with standard processes, but the pins are exposed after laser cutting causing potential short circuits and display failures
Solution Approach 1:
The patent introduces a chip on film as an intermediary component that carries both display pins and cell test pins. This mediator integrates the test pins within the chip structure rather than exposing them directly on the display cell, preventing short circuits while maintaining manufacturing compatibility. The chip on film acts as a buffer layer that protects the electrical connections during laser cutting and assembly processes.
Solution Approach 2:
The cell test pins are nested within the chip on film structure, specifically positioned in regions that are covered by the chip's protective film layer. This nesting arrangement allows the test pins to be housed inside the chip's physical boundaries, preventing exposure and short circuits while maintaining access for testing purposes through the chip's design.
2Productivity
If cell test pins are exposed after laser cutting, then manufacturing verification is possible, but erosion and short circuits occur causing display failures during credibility tests
Solution Approach 1:
The chip on film serves as a protective intermediary that shields the cell test pins from environmental erosion (water, oxygen) while maintaining electrical functionality. The film layer of the chip on film creates a barrier between the exposed pins and harmful external factors, preventing oxidation and short circuits that would otherwise occur with directly exposed pins during verification processes.
Solution Approach 2:
The patent applies protective measures beforehand by designing the chip on film with a film layer that covers and protects the cell test pins before they are exposed to environmental conditions. This prior cushioning prevents erosion and short circuit risks before they can manifest, ensuring reliability during credibility tests and verification processes.
3Reliability
If chip on film completely covers display pins and cell test pins, then short circuits are prevented, but the bonding region requires larger area
Solution Approach 1:
The chip on film is designed with different functional regions: a first region that covers the display pins for electrical connection, and a second region that extends to cover the cell test pins for protection. This local differentiation allows the bonding region to be optimized - covering only where necessary for each pin type - rather than requiring uniform coverage across the entire test area, thus reducing overall bonding region area while maintaining protection.
Solution Approach 2:
The patent utilizes the vertical dimension by stacking the chip on film over the display cell, with the chip positioned in a plane above the display surface. This dimensional arrangement allows the chip to cover the test pins vertically without requiring additional horizontal bonding area on the display cell plane, effectively using the Z-axis to solve the area constraint problem.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration ensures reliable lighting on-off tests without display failures by shielding cell test pins from erosion and preventing short circuits, ensuring proper functionality during credibility tests.
Implementation Method 1
an anisotropic conductive film located between the display cell and the chip on film
Data Source
AI summary
The disclosure provides a display panel and a display device, including a display cell. The display cell includes: a plurality of display pins and a plurality of cell test pins, which are arranged in a bonding region of the display cell; and a chip on film bonded to a side facing away from a display surface of the display cell. An orthographic projection of the chip on film on the display cell completely covers the display pins and the cell test pins.