Display Panel Test Shorting Bar Shared Trace Layout
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Solution Overview
Problem
Conventional liquid crystal display panel manufacturing faces challenges in reducing production costs and increasing substrate utilization due to dense array arrangements on mother substrates, leading to alignment issues and limited process margins.
Innovation Solution
The design of an array substrate with a peripheral circuit region where test shorting bars and wires share a common trace, reducing the overall layout area and improving substrate utilization, thereby enhancing alignment precision and reducing production costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If arrays are arranged densely on the mother substrate to increase utilization, then substrate utilization increases, but alignment precision deteriorates due to machines failing to catch alignment marks
Solution Approach 1:
The patent merges the function of the test shorting bar and the wire into a single integrated structure. The test shorting bar and wire share a common trace, eliminating the need for separate traces for each component. This integration reduces the overall space required in the peripheral circuit region, allowing arrays to be arranged more densely on the mother substrate without compromising alignment precision, as the reduced peripheral region creates adequate spacing between alignment marks and array forming regions.
2Ease of manufacture
If the distance between alignment marks and arrays is shortened to reduce production costs, then production costs decrease, but alignment precision deteriorates causing abnormal alignment
Solution Approach 1:
By integrating the test shorting bar and wire into a single structure with a shared common trace, the patent reduces the peripheral circuit region size. This reduction allows the distance between alignment marks and arrays to be minimized without causing alignment issues, as there is sufficient space for machine alignment even when arrays are positioned closer to alignment marks. This resolves the contradiction by enabling both cost reduction through shorter distances and maintained alignment precision.
3Productivity
If the peripheral circuit region is reduced to increase array density, then substrate utilization improves, but device complexity increases due to integrated test and signal functions
Solution Approach 1:
The integrated structure serves multiple functions: it acts as both a test shorting bar for detecting defects and a wire for signal transmission. The common trace can be used for both testing during manufacturing and for carrying signals during operation. This multi-functionality reduces the need for separate dedicated test structures and signal lines, thereby reducing overall circuit complexity while maintaining high array density on the substrate.
Data Source
AI summary
A display panel including a first substrate, a second substrate, and a liquid crystal layer. The first substrate comprises a display region and a peripheral circuit region adjacent to the display region, and the first substrate includes a pixel array, a plurality of test shorting bars, and a plurality of wires. The pixel array is disposed in the display region. The test shorting bars are disposed in the peripheral circuit region. The wires are disposed in the peripheral circuit region and electrically connected with the pixel array. Moreover, at least one wire and one of the test shorting bars respectively share a part for connecting with each other and forming a common trace. Additionally, the second substrate is disposed opposite to the first substrate. The liquid crystal layer is disposed between the first substrate and the second substrate.