Display Panel TFT Layout for Uniform Luminance Control
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Solution Overview
Problem
Mini/Micro-LED display panels experience non-uniform luminance due to parasitic capacitance between fan-out lines and power supply lines, causing variations in current flow and luminance across the display panel.
Innovation Solution
The display panel is designed with distinct channel width-to-length ratios for thin film transistors in different regions, adjusting the current difference between sub-pixels to minimize parasitic capacitance effects and ensure uniform luminance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If fan-out lines are arranged outside the display region, then routing complexity is reduced, but the distance between light-emitting diodes at the seam becomes excessively large
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional stacked architecture. Fan-out lines are routed in different layers (first substrate layer and second substrate layer) rather than all in the same plane, allowing lines to pass through intermediate regions without increasing horizontal distance between LEDs.
2Adaptability or versatility
If fan-out lines overlap power supply lines in the display region, then routing flexibility is improved, but parasitic capacitance increases causing non-uniform luminance
Solution Approach 1:
The patent divides the routing space into multiple discrete layers (first substrate layer, second substrate layer). Fan-out lines and power supply lines are segregated into different layers, eliminating their overlap in the display region while maintaining routing flexibility through vertical stacking.
Solution Approach 2:
By utilizing the vertical dimension with multiple substrate layers, the patent allows fan-out lines to be positioned above or below power supply lines, eliminating parasitic capacitance from overlapping while preserving routing flexibility through the additional spatial dimension.
3Power
If data voltage increases due to parasitic capacitance coupling, then current through light-emitting diode increases, but luminance uniformity deteriorates
Solution Approach 1:
The patent segments the signal routing into separate layers, isolating fan-out lines from power supply lines. This physical separation eliminates parasitic capacitance coupling, preventing unwanted voltage increases and maintaining stable, uniform luminance across all pixels.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method improves uniformity of luminance across the display panel by controlling current flow through sub-pixels, enhancing display quality.
Implementation Method 1
parasitic capacitance between fan-out lines and power supply lines, causing variations in current flow and luminance across the display panel
Implementation Method 2
potential of a data voltage transmitted through the fan-out line increase by coupling effect
Data Source
AI summary
A display panel includes a first display region and a second display region, wherein power supply lines and signal lines are arranged in each of the first and second display regions, each first sub-pixel is disposed in the first display region and electrically connected to the power supply line and the signal line, each second sub-pixel is disposed in the second display region and electrically connected to the power supply line and the signal line, in the second display region, an orthographic projection of the signal lines at least partially overlaps with that of the power supply lines, and when the display panel is in operation, a current difference between a first value of a first current flowing through a first thin film transistor and a second value of a second current flowing through a second thin film transistor is less than a preset threshold.