Display Panel Third Wire Spacing Reduces Signal Delay
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Solution Overview
Problem
Large-sized liquid crystal display panels experience signal transmission delays due to increased resistance and capacitance at the intersection of the gate line and data line, which is exacerbated by the small spacing between these lines.
Innovation Solution
A display panel design featuring a substrate with a gate line, a first insulating layer, a data line comprising a first wire, a second wire, and a third wire, where the third wire is intersected with and spaced apart from the gate line, and its ends pass through a second insulating layer to be electrically connected to the first and second wires, effectively increasing the distance between the third wire and the gate line, thereby reducing capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the spacing between the gate line and data line is reduced to increase resolution, then the resolution is improved, but the capacitance at the intersection increases causing signal transmission delay
Solution Approach 1:
The patent introduces a third wire (compensation wire) that passes through the second insulating layer to connect the first wire and second wire, creating a three-dimensional wire structure. This dimensional change allows the data line to be raised above the gate line level, increasing the vertical distance between intersecting lines and reducing parasitic capacitance at the intersection, thereby decreasing signal transmission delay while maintaining high resolution
Solution Approach 2:
The second insulating layer acts as an intermediary structure that physically separates and elevates the third wire above the gate line. This intermediary layer with appropriate dielectric properties reduces the electric field coupling between the data line and gate line, lowering parasitic capacitance and signal delay without affecting the planar resolution
2Area of stationary object
If the size of the printed substrate is increased for large-sized displays, then the display size is improved, but the resistance and capacitance of the circuit increase causing signal transmission delay
Solution Approach 1:
By raising the data line into the third dimension through the second insulating layer and connecting wires, the patent reduces the horizontal overlap area between gate lines and data lines at intersections. This vertical separation decreases parasitic capacitance, which is particularly beneficial for large-sized substrates where signal transmission delay becomes more pronounced
Solution Approach 2:
The patent applies the three-dimensional wire structure specifically at critical intersection points where gate lines and data lines cross. This localized application reduces capacitance at the most problematic areas (intersections) without requiring changes to the entire circuit layout, making it effective for large substrates while maintaining manufacturing feasibility
Data Source
AI summary
In some embodiments of the present disclosure, it is provided a display panel and a display. The space between the third wire and the gate line of the display panel is greater than the original thickness of the first insulating layer. Since the capacitance is inversely proportional to the space and the signal delay time is proportional to the capacitance, the signal delay time of the display panel can be reduced.