Display Panel Transistor Channel Width Optimization
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Solution Overview
Problem
As display panel sizes decrease with increasing resolution, maintaining electrical properties and displaying quality becomes challenging due to faulty design of components and layers, leading to decreased electrical performance.
Innovation Solution
A transistor structure design for a display panel with a semi-conductive layer having a channel width W and channel length L, where W is within the range (3.035-1.5) ≤ W - 0.008 × (Px × L × d) ≤ (3.035 + 1.5), ensuring consistent electrical properties and charging capability, even with reduced pixel size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the size of semiconductor device is decreased to meet down size requirements, then the display panel size is reduced, but the electrical properties and displaying quality deteriorate
Solution Approach 1:
The patent applies parameter changes by precisely controlling the channel width W and channel length L of the semi-conductive layer, along with their ratio W/L, to maintain optimal electrical properties. The specific mathematical relationship W = (3.035-1.5) ≤ W - 0.008 × (Px × L × d) ≤ (3.035 + 1.5) ensures that even as device size decreases, the electrical characteristics remain stable, resolving the contradiction between miniaturization and reliability.
2Measurement precision
If the patterns and sizes of metal layer and semiconductor device are reduced, then the display panel achieves higher resolution, but the electrical performance decreases
Solution Approach 1:
The patent resolves this contradiction by establishing precise parameter relationships for the semi-conductive layer. By controlling channel width W, channel length L, and their ratio according to the formula W = (3.035-1.5) ≤ W - 0.008 × (Px × L × d) ≤ (3.035 + 1.5), the invention enables higher resolution through smaller patterns while maintaining electrical performance through optimized dimensional parameters.
Solution Approach 2:
The patent applies local quality by optimizing specific regions of the transistor structure. The semi-conductive layer's channel region is precisely engineered with controlled width and length, creating locally optimized electrical characteristics that compensate for overall device miniaturization, thereby maintaining performance despite reduced size.
3Ease of manufacture
If faulty design of components and layers occurs, then manufacturing is simplified, but electrical performance and displaying quality deteriorate
Solution Approach 1:
The patent resolves this contradiction by providing clear, quantifiable parameter specifications for the semi-conductive layer. The mathematical relationship W = (3.035-1.5) ≤ W - 0.008 × (Px × L × d) ≤ (3.035 + 1.5) gives manufacturers precise design guidelines, eliminating guesswork and ensuring consistent electrical performance without requiring complex design iterations.
Data Source
AI summary
A display panel includes a first substrate, and the first substrate includes a base plate; a first conductive line disposed on the base plate and extending along the first direction; a second conductive line and a third conductive line disposed on the base plate and extending along the second direction; a contact pad positioned between the second and third conductive lines; a semi-conductive layer connecting the contact pad and the second conductive line, and the semi-conductive layer having a thickness d; and a pixel electrode connecting the contact pad. The semi-conductive layer has a channel width W (μm) and a channel length L (μm) between the contact pad and the second conductive line, and a pixel distance Px (μm) between the second and third conductive lines along the first direction, wherein the channel width W is conformed to the following equation:(3.035-1.5)≤W-0.008×(Px×Ld)≤(3.035+1.5).