Display Panel Transistor Terminal Arrangement for Parasitic Capacitance Compensation
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Solution Overview
Problem
The variation in parasitic capacitance due to displacement offsets during the manufacturing process of thin film transistors in display panels leads to uneven brightness and nonconformity in display quality.
Innovation Solution
The display panel design incorporates first and second pixel circuits with control transistors having terminals arranged in specific directions to compensate for parasitic capacitance variations caused by photomask offsets, ensuring uniform display quality by adjusting the relative positions of terminals in the transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If adjoined photomasks of a stepper exposure machine are used to fabricate thin film transistor arrays, then manufacturing efficiency is improved, but displacement offsets cause nonconformity in pattern locations leading to parasitic capacitance variation
Solution Approach 1:
The gate electrode is designed with an asymmetric structure where the gate source overlapping region and gate drain overlapping region have different widths. Specifically, the gate source overlapping region has a first width while the gate drain overlapping region has a second width that is different from the first width. This asymmetric design compensates for displacement offsets during exposure, ensuring that parasitic capacitance values remain consistent across different exposure shots despite variations in pattern location.
2Reliability
If gate and source electrodes are overlapped to form parasitic capacitance Cgs, then transistor switching function is achieved, but display uniformity deteriorates due to parasitic capacitance variation
Solution Approach 1:
The invention changes the geometric parameters of the gate electrode, specifically the width of overlapping regions with source and drain electrodes. By adjusting these dimensions, the parasitic capacitance values Cgs and Cgd are controlled to maintain consistent transistor characteristics across the display panel, thereby ensuring display uniformity while preserving the necessary switching function.
3Reliability
If gate and drain electrodes are overlapped to form parasitic capacitance Cgd, then transistor switching function is achieved, but display uniformity deteriorates due to parasitic capacitance variation
Solution Approach 1:
The invention changes the geometric parameters of the gate electrode, specifically the width of overlapping regions with source and drain electrodes. By adjusting these dimensions, the parasitic capacitance values Cgs and Cgd are controlled to maintain consistent transistor characteristics across the display panel, thereby ensuring display uniformity while preserving the necessary switching function.
4Productivity
If photomask displacement offset occurs during exposure, then manufacturing process continues, but parasitic capacitance values differ across exposure shots causing brightness nonconformity
Solution Approach 1:
The gate electrode is designed with an asymmetric structure where the gate source overlapping region and gate drain overlapping region have different widths. Specifically, the gate source overlapping region has a first width while the gate drain overlapping region has a second width that is different from the first width. This asymmetric design compensates for displacement offsets during exposure, ensuring that parasitic capacitance values remain consistent across different exposure shots despite variations in pattern location.
Data Source
AI summary
A display panel includes a plurality of scan lines, a plurality of data lines, a plurality of power lines, a plurality of light emitting units, a plurality of first pixel circuits and a plurality of second pixel circuits. The plurality of light emitting units are arranged in an array and adapted to display different colors. In the organic light emitting units with the same color, some parts are connected to the first pixel circuits, and other parts are connected to the second pixel circuits. A first terminal and a second terminal of a first control transistor in the first pixel circuit are sequentially arranged on a forward direction of a first direction, and a first terminal and a second terminal of a second control transistor in the second pixel circuit are sequentially arranged on a reverse direction of the first direction.