Display Panel Transistor Layout for Narrow Bezel Clock Routing
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Solution Overview
Problem
Existing display panels face challenges in reducing the non-display area (bezel) width due to the limitations in the design of clock lines, connecting lines, and transistor arrangement, which hinder the achievement of a narrow bezel.
Innovation Solution
The display panel design includes a novel arrangement of transistors and connecting lines, with alternating clock lines and staggered transistor positions, and a bent shape in the connecting lines to optimize space utilization, allowing for a reduced non-display area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If transistors and connecting lines are arranged in a conventional manner, then the layout is simple, but the non-display area width cannot be reduced
Solution Approach 1:
The patent applies dimensionality change by arranging transistors in two rows above and below the clock lines, and routing connecting lines in a stepped pattern across multiple rows. This transforms the conventional linear arrangement into a two-dimensional distributed layout, reducing the non-display area width while maintaining electrical connectivity through the virtual reference line separation.
Solution Approach 2:
The patent segments the transistor arrangement into two distinct rows (first row above clock lines, second row below clock lines) and divides connecting lines into multiple segments that step across different rows. This segmentation allows each component to be positioned optimally for signal transmission while minimizing the overall footprint of the non-display area.
2Length of stationary object
If clock lines and connecting lines are arranged to minimize space, then the non-display area is reduced, but signal transmission reliability may be compromised
Solution Approach 1:
The patent introduces a virtual reference line as an intermediary conceptual boundary that separates first group transistors from second group transistors, and similarly separates first group connecting lines from second group connecting lines. This virtual reference line serves as a mediator for organizing the spatial arrangement while ensuring that signal transmission paths remain reliable through structured routing across the reference line.
Solution Approach 2:
By distributing connecting lines across multiple rows in a stepped pattern rather than concentrating them in a single plane, the patent maintains signal transmission reliability through multiple parallel paths while reducing the non-display area width. The two-row transistor arrangement above and below clock lines provides redundant signal routing options.
Data Source
AI summary
A display panel includes a plurality of pixels, a stage including a plurality of transistors, a plurality of clock lines electrically connected to the stage, and a plurality of connecting lines that connect the plurality of clock lines to the plurality of transistors. The plurality of transistors include a plurality of first group transistors connected to (2N−1)th pixels arranged in the first direction among the plurality of pixels, and a plurality of second group transistors connected to 2N-th pixels arranged in the first direction among the plurality of pixels. The plurality of first group transistors and the plurality of second group transistors are spaced apart from each other with respect to a virtual reference line that line extends in a second direction crossing the first direction.