Display Panel Shift Register Layout for Narrow-Frame Scan Charging
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Solution Overview
Problem
Existing display panel technologies face challenges in increasing pre-charging and charging times while maintaining a narrow frame design due to the need for additional start signal lines, which occupy space in the non-display region.
Innovation Solution
A display panel design with a reduced number of trigger signal lines and optimized connections of clock signal lines to shift registers, allowing for increased pre-charging and charging times while minimizing the non-display region's size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of moving object
If the quantity of clock signal lines is increased to extend pre-charging and charging time, then the display effect is improved, but the quantity of start signal lines must also increase correspondingly, occupying more space in the non-display region
Solution Approach 1:
The patent merges the functions of multiple start signal lines into a single start signal line by utilizing the cascaded shift register structure. The shift registers propagate the scan signal through multiple stages, eliminating the need for multiple independent start signal lines while maintaining the extended pre-charging and charging time achieved through increased clock signal lines.
Solution Approach 2:
The single start signal line serves multiple functions by triggering the cascaded shift register structure, which then distributes scan signals to multiple scan lines. This multi-functional approach allows one start signal line to replace what would traditionally require multiple start signal lines, reducing the non-display region space while maintaining display performance.
2Duration of action of moving object
If the quantity of start signal lines is increased to match the increased clock signal lines, then the pre-charging and charging time can be maintained, but the frame width increases, preventing narrow frame design
Solution Approach 1:
The patent combines multiple start signal functions into a single start signal line by using the shift register cascade structure. This merging allows the pre-charging and charging time to be extended through additional clock signal lines without requiring proportional increases in start signal lines, thereby maintaining narrow frame width.
Solution Approach 2:
The patent transitions from a one-to-one correspondence between start signal lines and clock signal lines to a many-to-one relationship enabled by the cascaded shift register structure. This dimensional change in signal distribution allows extended pre-charging time through multiple clock lines while maintaining a single start signal line, achieving narrow frame design.
3Reliability
If more signal lines are added to the non-display region, then the display performance is improved, but the manufacturing complexity and cost increase
Solution Approach 1:
The patent merges multiple start signal lines into a single start signal line by utilizing the cascaded shift register structure. This reduction in signal line quantity decreases manufacturing complexity and cost while maintaining improved display performance through extended pre-charging and charging time achieved via additional clock signal lines.
Data Source
AI summary
The present disclosure provides a display panel and a driving method. The display panel includes a display region, including a plurality of scan lines, and a non-display region. The non-display region includes a first non-display region including a trigger signal line, a plurality of first-clock signal lines from a first first-clock signal line to a k-th first-clock signal line, a plurality of second-clock signal lines from a first second-clock signal line to a k-th second-clock signal line, and n levels of cascaded shift registers; the plurality of first-clock signal lines is electrically connected to k levels of shift registers in sequence, respectively; the plurality of second-clock signal lines is electrically connected to the k levels of shift registers in sequence, respectively; and the trigger signal line is electrically connected to shift registers from a first level to a k-th level and from an (n−k+1)-th level to an n-th-level.