Display Panel Vernier Alignment for Conductive Adhesive Bonding
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Solution Overview
Problem
Manufacturing processes for electronic apparatuses face reliability issues due to misalignment of electronic components caused by vibration, leading to deteriorated connection reliability.
Innovation Solution
Incorporation of a vernier mark on the display panel to facilitate precise alignment of a conductive adhesive member with pads, ensuring stable electrical connection between the display panel and circuit board.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the conductive adhesive member is positioned close to the pad and signal line for compact design, then the device complexity is reduced, but the risk of contamination during bonding increases
Solution Approach 1:
The vernier mark serves as an intermediary reference element positioned between the conductive adhesive member and the pad/signal line. This intermediary allows the bonding process to be aligned with sub-50µm precision, ensuring the conductive adhesive member maintains safe distance from sensitive components while achieving compact overall design. The vernier mark enables precise positioning without requiring direct visual alignment between the adhesive member and pad.
Solution Approach 2:
The vernier mark is pre-formed on the substrate before the bonding process. This preliminary action establishes a fixed reference framework that guides the subsequent alignment of the circuit board and conductive adhesive member. By having the reference marks ready in advance, the system eliminates the need for complex real-time alignment mechanisms, reducing both device complexity and contamination risk.
2Measurement precision
If vernier marks are formed near the pad and signal line for precise alignment, then the measurement precision is improved, but the risk of contamination during bonding increases
Solution Approach 1:
The alignment reference system is segmented into two distinct components: vernier marks formed on the substrate and corresponding reference marks on the circuit board. This segmentation allows the vernier marks to be positioned in safe areas away from pads and signal lines, eliminating contamination risk while maintaining measurement precision. The segmented reference system distributes the alignment function across multiple locations rather than concentrating it near sensitive components.
Solution Approach 2:
The vernier marks act as intermediary reference elements that mediate between the substrate and the circuit board alignment process. By positioning these intermediary marks in safe areas, the system achieves precise alignment (sub-50µm) without placing reference elements near contamination-prone areas. The intermediary vernier marks transfer the alignment function from sensitive regions to safe regions.
3Measurement precision
If the bonding process uses high precision alignment for sub-50µm accuracy, then the measurement precision is improved, but the manufacturing complexity increases
Solution Approach 1:
The vernier mark and reference mark system enables self-alignment during the bonding process. The overlapping patterns of vernier marks create visual or detectable references that guide the positioning of the circuit board and conductive adhesive member without requiring complex external alignment equipment. The system serves its own alignment function through the geometric relationship between vernier and reference marks, eliminating the need for sophisticated alignment machinery.
Solution Approach 2:
The vernier marks and reference marks are pre-formed with precise geometric relationships before bonding. This preliminary action establishes the alignment framework in advance, so that during bonding, the system only needs to follow the pre-established geometric cues rather than performing complex real-time calculations or adjustments. The pre-formed marks reduce manufacturing complexity by shifting the precision requirement to the mark formation process rather than the bonding process.
Data Source
Figure 1A
Figure 1B
Figure 1C
AI summary
An electronic apparatus comprising a display panel, which comprises: a base substrate comprising an active area and a peripheral area adjacent to the active area; pixels on the active area; pads on the peripheral area and arranged in a first direction; signal lines connecting the pixels to the pads; and vernier marks on the peripheral area and spaced apart from the pad and the signal lines, a circuit board on the display panel and comprising: a base film; and leads on the base film and overlapping with the corresponding pads in a plan view; and a conductive adhesive member extending in the first direction and between the display panel and the circuit board to connect the pads to the leads. Each of the vernier marks comprises a plurality of patterns spaced apart from each other, a portion of the conductive adhesive member overlaps at least one of the plurality of patterns. And in a second direction crossing the first direction, a width from a lowermost pattern to an uppermost pattern among the plurality of patterns is 100 µm or more and 450 µm or less.