Display Panel Pixel Circuit With Vertical Interconnect Layout
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Solution Overview
Problem
The challenge is to design a display panel that reduces pixel layout space to meet the demands for high-resolution and high-definition displays, where the increasing pixel density requires innovative arrangements to maintain performance.
Innovation Solution
The display panel incorporates a substrate with an active layer and sub-pixels, featuring a pixel circuit with a first and second transistor, where the second electrode of the second transistor is connected to a light-emitting element through a connecting portion disposed away from the substrate, allowing for efficient signal transmission and reduced layout space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If pixel density is increased to achieve high-resolution display, then display quality is improved, but pixel layout space becomes smaller and more constrained
Solution Approach 1:
The patent applies dimensionality change by routing the first connecting portion (connecting the first and second transistors) through the active layer to the anode of the light-emitting element, rather than keeping all connections within the same planar layer. This three-dimensional wiring approach allows signals to pass through vertical layers, effectively utilizing the Z-dimension to reduce lateral space requirements and enable higher pixel density while maintaining display quality.
2Area of stationary object
If pixel layout space is reduced to increase pixel density, then high-resolution display is achieved, but signal transmission efficiency may be compromised
Solution Approach 1:
The patent resolves this contradiction by implementing a vertical signal transmission path where the first connecting portion extends through the active layer to reach the anode of the light-emitting element. This three-dimensional connection maintains reliable signal transmission by providing a direct electrical pathway through layers, avoiding the need for longer lateral connections that would be required in a purely planar configuration, thus preserving signal efficiency while reducing pixel layout space.
Solution Approach 2:
The patent applies nesting by integrating the first connecting portion within the structure of the light-emitting element itself, specifically connecting to the anode. This nested configuration allows the connecting portion to be housed within or closely integrated with the light-emitting element's structure, reducing the need for separate external connection structures and maintaining compact pixel design while ensuring reliable signal transmission.
Data Source
AI summary
A display panel and a display device are provided. In the display panel, a first electrode of a first transistor is electrically connected to a first signal line, a second electrode of the first transistor is electrically connected to a first electrode of a second transistor through a first connecting portion, a second electrode of the second transistor is electrically connected to a light-emitting element, and the first connecting portion is disposed on one side, away from a substrate, of an active layer, which facilitates reducing a layout space of sub-pixels, to facilitate adaptation to the demands for displaying in high resolution and high definition.