Display Panel Via Structure for Reliable TFT Source-Drain Contact

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In the manufacturing of thin film transistors with a bottom gate structure, metal wires often experience poor contact or breakage when bonded with the semiconductor layer due to poor contact or structural weaknesses.

Innovation Solution

The proposed solution involves a display panel structure with a dielectric layer that includes a first via hole connected to the source or drain region and a second via hole located on top of the first via hole, with the aperture of the second via hole being larger than that of the first via hole. This configuration reduces the steepness of the via holes and forms a buffer structure that prevents metal wires from breaking during bonding.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a single via hole with small aperture is used to connect metal wires to semiconductor layer, then the structure is simple and manufacturing is easy, but the metal wires are prone to breakage due to poor contact and structural weakness

Engineering Contradiction:
Improvemetal wire contact reliabilityVSAvoidvia hole structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The via hole structure is segmented into two parts: a first via hole with smaller aperture connected to the semiconductor layer, and a second via hole with larger aperture at the top connected to the metal wire. This segmentation creates a buffer structure that improves contact reliability while distributing mechanical stress, preventing wire breakage without excessive complexity

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The via hole structure transitions from a single-dimensional small aperture to a two-dimensional graded aperture structure. The aperture size varies along the vertical dimension, creating a gradual transition from small to large aperture that reduces stress concentration and improves mechanical reliability

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Manufacturing precision

If via holes with steep walls are formed for precise alignment, then manufacturing precision is improved, but metal wires are more prone to breakage during bonding

Engineering Contradiction:
Improvevia hole alignment precisionVSAvoidmetal wire bonding strength
Core Design Contradiction:
Manufacturing precisionVSStrength

Solution Approach 1:

The via hole aperture parameter is changed along the vertical direction, creating a graded structure where the aperture increases from bottom to top. This parameter change maintains precise alignment capability through the smaller bottom aperture while improving wire bonding strength through the larger top aperture that provides better mechanical support

Inventive Principle:
Principle #35Parameter changes

3Reliability

If a buffer structure with graded aperture is formed, then metal wire bonding reliability is improved, but the manufacturing process becomes more complex

Engineering Contradiction:
Improvemetal wire bonding reliabilityVSAvoidvia hole fabrication ease
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The via hole formation process is segmented into distinct stages corresponding to the first and second via holes with different apertures. This segmentation allows each portion to be optimized independently while maintaining overall manufacturability through systematic process steps

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS12218208B2Display panel, display panel manufacturing method, and display device
Publication Date: 2025.02.04 HKC CORP LTD
  • US12218208B2 patent drawing
  • US12218208B2 patent drawing
  • US12218208B2 patent drawing

AI summary

The present application discloses a display panel, a display panel manufacturing method, and a display device. The display panel includes a source region and a drain region. A dielectric layer covering the source region and the drain region is provided with a first via hole and a second via hole separately. The first via hole is connected to the source region or the drain region, the second via hole is located on the top of the first via hole and is in communication with the first via hole, and an aperture of the second via hole is larger than an aperture of the first via hole.