Display Panel Layout With Direct Via Initialization Connection

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Solution Overview

Problem

In display panels, the connection of transistors to initialization lines requires additional connecting members, which can cause mutual interference with other signal lines and manufacturing residues, affecting display performance.

Innovation Solution

The display panel design eliminates the need for additional connecting members by directly connecting the sixth electrode area of the third transistor to the initialization line through a via hole, positioning the initialization line between the reset and gate lines, reducing parasitic capacitance and avoiding manufacturing residues.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If an additional connecting member is used to connect the transistor to the initialization line, then the electrical connection is established, but mutual interference with other signal lines occurs and manufacturing residues are generated

Engineering Contradiction:
Improveelectrical connectionVSAvoidmutual interference and manufacturing residues
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The initialization line is merged with the gate line structure, allowing the third transistor to share the gate line as its connection path to the initialization line. This integration eliminates the need for separate connecting members and reduces manufacturing complexity while avoiding interference with other signal lines.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The gate line serves multiple functions: it acts as both the control signal line for the first transistor and as the connection path (initialization line) for the third transistor. This multi-functionality reduces the total number of signal lines and connecting members required in the display panel.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If more transistors and signal lines are added to sub-pixels, then the display functionality is enhanced, but the device complexity increases

Engineering Contradiction:
Improvedisplay functionalityVSAvoidnumber of transistors and signal lines
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The gate line is designed to serve dual purposes: as the gate control line for the first transistor and as the initialization line for the third transistor. This multi-functional design reduces the total number of signal lines required while maintaining enhanced display functionality through multiple transistors.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the initialization line function into the existing gate line structure, eliminating the need for separate dedicated initialization lines. This consolidation reduces device complexity while preserving the functionality of multiple transistors for enhanced display performance.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS12581814B2Display panel with improved display effect and manufacturing method thereof, and display device
Publication Date: 2026.03.17 ORDOS YUANSHENG OPTOELECTRONICS
  • US12581814B2 patent drawing
  • US12581814B2 patent drawing
  • US12581814B2 patent drawing

AI summary

Provided are a display panel and a manufacturing method thereof, and a display device. The display panel includes a base substrate and a plurality of sub-pixels. At least one sub-pixel includes a light-emitting element; a first transistor; a capacitor including a first electrode and a second electrode plate; a second transistor including a second active layer including a third and a fourth electrode area, and a second channel area; and a third transistor including a third active layer, and a third gate electrode connected to a reset line, the third active layer including a fifth electrode area, a sixth electrode area directly connected to an initialization line via a via hole, and a third channel area. An orthographic projection of the initialization line on the base substrate is located between orthographic projections of the reset line and the gate line on the base substrate.