Display Panel Via Taper Angle Control
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Solution Overview
Problem
In high-resolution display panels, the formation of chamfers during the etching process for via creation can lead to incomplete filling or discontinuous conductive layers due to different insulating layers having varying coating conditions, affecting the quality of the display panel.
Innovation Solution
The design of passivation layers with specific taper angles on the sidewalls of vias ensures a smooth junction, preventing electrode layer breakage and maintaining low impedance by adjusting the etching rates of multiple passivation films to control the angle difference between the first and second taper angles, typically keeping it between 0° and 30°.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple insulating layers with different coating conditions are used to achieve high resolution display panel structure, then the display resolution is improved, but chamfer formation occurs during etching which causes incomplete via filling or discontinuous conductive layers
Solution Approach 1:
The patent changes the physical parameters of the passivation layers by controlling their thickness and taper angles. Specifically, the first passivation layer has a first taper angle and the second passivation layer has a second taper angle, with the angle difference controlled between 0-30 degrees. This parameter optimization prevents chamfer formation and ensures complete via filling while maintaining high display resolution
Solution Approach 2:
The patent uses a composite structure of multiple passivation layers (first passivation layer and second passivation layer) with different materials or properties. Each layer has specific thickness and taper angle characteristics that work together to prevent chamfer formation during etching, solving the via filling problem while preserving the high resolution display structure
2Measurement precision
If multiple insulating layers with different coating conditions are used to achieve high resolution display panel structure, then the display resolution is improved, but the conductive layer continuity is compromised due to chamfer formation
Solution Approach 1:
The patent optimizes the taper angles of the passivation layers as key parameters. The first passivation layer has a first taper angle and the second passivation layer has a second taper angle, with their difference controlled within 0-30 degrees. This parameter control ensures smooth via walls that maintain conductive layer continuity while supporting high resolution display requirements
Solution Approach 2:
Instead of trying to prevent chamfer formation by modifying the etching process directly, the patent inverts the approach by designing the passivation layers with specific taper angles that naturally prevent chamfer formation. The controlled angle difference between layers creates smooth transitions that maintain conductive layer integrity
3Ease of manufacture
If the taper angle difference between passivation layers is not controlled, then the manufacturing process is simpler, but the contact impedance increases and electrode layer breaks occur
Solution Approach 1:
The patent identifies the taper angle difference as a critical parameter to control for reliability. By specifying that the difference between the first taper angle and second taper angle should be 0-30 degrees, the patent ensures smooth via walls that prevent electrode layer breaks and maintain low contact impedance, while still allowing for practical manufacturing processes
Data Source
AI summary
A display device including a TFT substrate and a display layer is provided. The TFT substrate includes a substrate, a gate layer, a semiconductor layer, a gate dielectric layer, a first electrode layer, a first passivation layer, a second passivation layer, and a second electrode layer. A via penetrates the first passivation layer and the second passivation layer to expose a portion of the first electrode layer, and the via has a sidewall. The second electrode layer is electrically connected to the first electrode layer through the via, the first passivation layer has a first edge on the sidewall of the via, the second passivation layer has a second edge on the sidewall of the via, and the first edge and the second edge are separated by a distance in the range of 500-2000 Å.


