Display Panel Voltage Routing for Wearable Signal Stability
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Solution Overview
Problem
Existing display panels for wearable devices face issues with signal stability and uniformity due to increased resistance in VDD lines and overlapping areas between signal lines, affecting the brightness and reliability of OLED displays.
Innovation Solution
A display panel design featuring at least two first driving voltage lines symmetrically disposed relative to gate driving signal lines, with a COP (Chip On PI) + FOP (FPC On PI) architecture, where the driving chip bonding area is between the bending and flexible printed circuit bonding areas, and the gate driving signal lines are optimized to reduce load differences and overlapping areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If VDD lines are extended to cover the display area, then the driving voltage signal can reach the display region, but the line resistance increases causing signal instability and non-uniformity
Solution Approach 1:
The patent divides the VDD signal transmission path into multiple segments by introducing intermediate voltage lines (ELVDD1, ELVDD2) that connect to the main VDD line at different positions. This segmentation allows the voltage signal to be distributed through multiple shorter paths rather than one long path, reducing the overall resistance and improving signal stability across the display area.
Solution Approach 2:
The patent transitions from a single linear VDD line configuration to a multi-dimensional network of voltage lines by adding intermediate ELVDD lines that branch off at different locations and extend in different directions. This dimensional expansion creates a distributed voltage distribution network that reduces resistance by providing multiple parallel conduction paths.
2Adaptability or versatility
If gate driving signal lines and data signal lines are routed through the bending area, then the display panel can achieve flexible wearable application, but the overlapping area between signal lines increases causing signal interference and load imbalance
Solution Approach 1:
The patent employs asymmetric routing strategies where gate driving signal lines and data signal lines are deliberately positioned at different locations within the bending area. The gate lines are routed along one side while data lines are routed along the opposite side, creating an asymmetric layout that minimizes overlapping and interference while maintaining flexibility.
Solution Approach 2:
The patent extracts the problematic overlapping region by separating the routing paths of gate driving signal lines and data signal lines. Instead of allowing them to share the same bending area path, the design routes them through different spatial channels, effectively removing the harmful interaction between these signal lines.
3Adaptability or versatility
If signal lines are routed through the bending area to connect driving chip and display area, then the flexible display structure is achieved, but the resistance and signal loss increase
Solution Approach 1:
The patent applies local quality optimization by introducing intermediate voltage lines at specific locations within the bending area where signal degradation is most critical. These ELVDD lines are strategically positioned to provide local voltage reinforcement, compensating for signal loss in high-resistance regions without requiring complete redesign of the entire routing structure.
Solution Approach 2:
The intermediate voltage lines (ELVDD1, ELVDD2) act as mediators between the main VDD line and the display area. These intermediary conductors provide additional conduction paths that reduce the overall resistance and signal loss by distributing the voltage signal through multiple intermediate stages rather than a single direct path.
Data Source
AI summary
Disclosed are a display panel and a display device. The display panel includes: at least one group of gate driving signal lines, the gate driving signal lines starting from the driving chip bonding area and going around the display area after passing through the bending area; and at least two first driving voltage lines, the at least two first driving voltage lines respectively starting from the flexible printed circuit bonding area, going through the bending area after passing through two sides of the driving chip bonding area, and extending to be close to the display area, and the at least two first driving voltage lines are respectively at two sides of the at least one group of gate driving signal lines.