Display Panel Peripheral Wiring Heat Management
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Solution Overview
Problem
Liquid crystal display devices employing gate driver monolithic technology experience excessive heat generation in the peripheral regions due to the configuration of gate drive circuits and main lines, which can lead to thermal issues and inefficiencies.
Innovation Solution
The display apparatus incorporates a specific configuration of clock main lines, outer and inner main lines, and branch wiring lines in the peripheral regions, with varying resistance values and overlapping areas to efficiently distribute signals and reduce heat generation, including a control circuit to manage these lines and ensure effective signal supply to the gate drive circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a gate drive circuit and main lines are configured in the peripheral region to supply signals to the gate drive circuit, then the signal supply function is improved, but excessive heat is generated in the peripheral region
Solution Approach 1:
The peripheral region is divided into multiple unit regions, with each unit region containing a subset of the gate drive circuit stages. This segmentation distributes the heat generation across multiple smaller regions rather than concentrating it in one area, while maintaining the signal supply function to all stages.
Solution Approach 2:
Different unit regions are configured with different resistance values for their respective branch wiring lines. Unit regions closer to the terminal portion have smaller resistance values, while those farther away have larger resistance values. This local variation in resistance optimizes current distribution and reduces overall heat generation in the peripheral region.
2Adaptability or versatility
If multiple clock main lines are provided to supply different phase clock signals to multiple stages, then the signal distribution capability is improved, but the device complexity increases
Solution Approach 1:
Multiple clock main lines are merged into a single clock main line by strategically positioning contact holes at overlapping regions. This merging reduces the number of separate wiring lines needed while maintaining the ability to supply different phase clock signals to multiple stages through the shared clock main line infrastructure.
Solution Approach 2:
The patent utilizes the vertical dimension by forming contact holes that extend through insulating layers to connect branch wiring lines to main lines. This three-dimensional wiring approach allows multiple signal paths to be established without requiring proportionally more planar wiring space, thereby reducing overall device complexity.
3Ease of operation
If branch wiring lines are provided in each unit region to connect main lines, then the signal connectivity is improved, but the manufacturing precision requirements increase
Solution Approach 1:
Branch wiring lines in different unit regions are designed with different resistance values based on their position. Unit regions closer to the terminal portion have branch wiring lines with smaller resistance values, while those farther away have larger resistance values. This local optimization simplifies the overall resistance matching problem by allowing each unit region to be independently tuned.
Solution Approach 2:
The resistance values of branch wiring lines are systematically varied across different unit regions rather than maintaining uniform resistance. This parameter change approach allows the system to achieve proper signal distribution and heat management while using standard manufacturing processes, thereby reducing the stringency of manufacturing precision requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses heat generation in the peripheral regions, enhancing the performance and reliability of the display apparatus by optimizing signal distribution and reducing thermal issues.
Implementation Method 1
a resistance value of the at least one branch wiring line between the inner main line and the outer main line in the first unit region is smaller than a resistance value of the at least one branch wiring line between the inner main line and the outer main line in the second unit region
Implementation Method 2
n number of clock main lines being configured to supply n number of types of clock signals having different phases from one another to the plurality of stages included in the shift register
Data Source
AI summary
A display apparatus includes: a display panel including a display region, a first peripheral region, and a second peripheral region; and a circuit substrate. The display panel includes a gate drive circuit, n number of clock main lines, an outer main line and an inner main line, and a plurality of branch wiring lines. The first peripheral region includes a plurality of unit regions. The plurality of unit regions includes a first unit region and a second unit region. A resistance value of the at least one branch wiring line between the inner main line and the outer main line in the first unit region is smaller than a resistance value of the at least one branch wiring line between the inner main line and the outer main line in the second unit region.