Display Panel Wiring Layout for Parasitic Capacitance Reduction
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Solution Overview
Problem
In high-definition display panels using organic electroluminescence (EL) devices, parasitic capacitance between adjacent wirings leads to degradation in display quality and increased power consumption due to reduced pixel spacing.
Innovation Solution
The layout of adjacent wirings in the display panel is designed such that their thickness directions differ, increasing the distance between them and reducing parasitic capacitance, with two wirings of the same type being disposed in a common region between adjacent pixels, each with a unique layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If pixel spacing is reduced to increase display resolution, then display quality is improved, but parasitic capacitance between adjacent wirings increases
Solution Approach 1:
The patent applies dimensional change by transitioning from a two-dimensional planar layout to a three-dimensional stacked arrangement of wirings. Specifically, adjacent wirings are positioned in different layers (first wiring layer and second wiring layer) separated by an insulating film, effectively increasing the distance between them in the thickness direction while maintaining close spacing in the planar view for high-resolution display.
Solution Approach 2:
The patent implements nesting by placing wirings of different types in alternating layers. The first wirings and second wirings are interleaved in the thickness direction, with insulating films separating the layers. This nested arrangement allows multiple wirings to occupy the same horizontal footprint area while being vertically separated, reducing parasitic capacitance between adjacent signal lines.
2Measurement precision
If wirings are positioned closer together to reduce pixel spacing, then display resolution is improved, but crosstalk between adjacent wirings increases
Solution Approach 1:
The patent introduces an insulating film as an intermediary between adjacent wirings. This insulating film acts as a mediator that electrically isolates the first wirings from the second wirings, preventing direct electrical interaction and crosstalk while allowing the wirings to be positioned in close proximity for high-resolution display.
Solution Approach 2:
By separating wirings in the thickness dimension through layered construction with insulating films, the patent reduces crosstalk without compromising the reduced pixel spacing achieved in the planar dimension. The vertical separation provides electrical isolation while maintaining horizontal closeness for high resolution.
3Productivity
If mirror-image arrangement of pixel circuits is used to improve yield, then manufacturing yield is improved, but parasitic capacitance between adjacent wirings increases
Solution Approach 1:
The patent resolves the contradiction by utilizing the thickness dimension to separate wirings. Even though mirror-image arrangements place wirings in close proximity in the planar view, the layered structure with insulating films provides vertical separation, maintaining high manufacturing yield while reducing parasitic capacitance through three-dimensional spatial arrangement.
Data Source
AI summary
A display panel includes: a plurality of first wirings extending in a row direction; a plurality of second wirings extending in a column direction; and a plurality of pixels each arranged in proximity to an intersection of each of the first wirings and each of the second wirings. Two wirings of the plurality of first wirings or two wirings of the plurality of second wirings are disposed in a common region interposed between two pixels next to each other, and layouts of the respective two wirings in a thickness direction are different from each other at least in a part of each of the layouts.