Multi-Layer Conductive Patterns for Display Peripheral Area
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Solution Overview
Problem
Existing display apparatuses face challenges in reducing the size of the peripheral area while maintaining improved display quality, particularly due to high resistance of signal lines and parasitic capacitance.
Innovation Solution
The display apparatus incorporates a multi-layer conductive pattern structure in the peripheral area, with signal lines formed from multiple conductive pattern layers and connecting lines formed as the uppermost or lowermost layer, reducing resistance and parasitic capacitance, and includes a gate signal generator and power supply lines to enhance display performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If signal lines are formed using single conductive layer, then manufacturing process is simple, but resistance is high
Solution Approach 1:
The signal lines are formed by stacking multiple conductive pattern layers (first, second, and third conductive pattern layers) to create a composite conductive structure. This multi-layer composite approach reduces the overall resistance of the signal lines while maintaining manufacturing feasibility through sequential layer formation processes.
Solution Approach 2:
The invention transitions from a single-layer conductive structure to a multi-layer stacked structure, adding the vertical dimension to the conductive path. By forming conductive patterns in multiple layers that overlap and connect, the signal transmission path is enhanced with reduced resistance without significantly complicating the horizontal layout.
2Adaptability or versatility
If connecting lines are placed in middle layers, then routing flexibility is improved, but parasitic capacitance increases
Solution Approach 1:
The conductive pattern structure is segmented into distinct functional layers: connecting lines are isolated in the lowermost or uppermost layers while signal lines occupy intermediate layers. This segmentation allows connecting lines to extend in the first direction without overlapping signal lines, reducing parasitic capacitance while maintaining routing flexibility through the available layer assignments.
Solution Approach 2:
Insulating layers are introduced as intermediary elements between the connecting lines and signal lines. These insulating layers (first, second, and third insulating layers) physically separate the conductive elements, minimizing parasitic capacitance coupling while still allowing the connecting lines to route signals effectively to the gate signal generator.
3Area of stationary object
If peripheral area is reduced, then device size is minimized, but signal line resistance increases
Solution Approach 1:
The signal lines utilize multiple vertical layers to reduce resistance, compensating for the reduced horizontal path length available in the minimized peripheral area. The multi-layer stacking provides parallel conductive paths that reduce overall resistance without requiring additional horizontal space.
Solution Approach 2:
Multiple conductive pattern layers are combined to form a composite low-resistance pathway for signals. This composite structure allows the peripheral area to be minimized while maintaining low signal line resistance through the enhanced conductive cross-section provided by the stacked layers.
4Reliability
If multiple conductive pattern layers are used, then resistance is reduced, but device complexity increases
Solution Approach 1:
The multi-layer conductive pattern structure serves multiple functions simultaneously: it reduces signal line resistance through stacked conductive paths, provides routing flexibility for connecting lines in outer layers, and enables spatial separation to minimize parasitic capacitance. This universal structure handles multiple electrical requirements without requiring separate dedicated structures for each function.
Data Source
AI summary
A display apparatus includes a base substrate that includes a display area in which pixels are formed and a peripheral area that is a non-display area that surrounds the display area, a first conductive pattern layer disposed on the base substrate, a first insulating layer disposed on the first conductive pattern layer, a second conductive pattern layer disposed on the first insulating layer, a second insulating layer disposed on the second conductive pattern layer, and a third conductive pattern layer disposed on the second insulating layer. The peripheral area includes a first wiring area and a circuit area.