Display Substrate Pin Height Layout to Prevent Probe Damage
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Solution Overview
Problem
During the electronic testing of display substrates, such as OLED displays, there is a risk of bruising or scratching signal access pins due to the proximity of test signal access pins, leading to yield loss and potential short-circuits, as testing devices may inaccurately contact signal access pins instead of test signal access pins.
Innovation Solution
A display substrate design featuring a height difference between the test signal access pin layer and the signal access pin layer, with the test signal access pin layer being higher than the signal access pin layer, ensuring that the testing device only contacts the test signal access pin layer, thereby preventing damage to the signal access pin layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the test probe contacts the test signal access pin during electronic testing, then the test signal can be accessed, but the signal access pin may be inadvertently damaged due to misalignment
Solution Approach 1:
The patent introduces a vertical height dimension to separate the test signal access pin from the signal access pin. The test signal access pin layer is positioned at a different height (closer to the display region) than the signal access pin layer, creating a three-dimensional spatial separation that prevents the test probe from contacting the signal access pin during testing operations.
Solution Approach 2:
The patent introduces an insulating layer as an intermediary structure between the test signal access pin and the signal access pin. This insulating layer physically separates the two pin types and prevents direct contact between the test probe and the signal access pin, thereby protecting the signal access pin from damage during testing.
2Productivity
If the test probe is positioned to contact the test signal access pin, then testing can be performed, but misalignment may cause the probe to contact and damage the signal access pin
Solution Approach 1:
By positioning the test signal access pin at a different vertical height from the signal access pin, the patent creates a safe operational zone for the test probe. This height difference ensures that during normal testing operations, the probe only contacts the elevated test signal access pin and cannot reach the lower signal access pin, eliminating the harmful mechanical damage effect.
Solution Approach 2:
The insulating layer acts as a protective barrier that is in place before testing occurs. This pre-established protective structure prevents potential mechanical damage to the signal access pin by absorbing or deflecting any inadvertent probe contact, thereby cushioning against harmful effects before they can occur.
3Area of stationary object
If the test signal access region is placed adjacent to the signal access region for compact layout, then device area is reduced, but the risk of probe misalignment damage increases
Solution Approach 1:
The patent maintains the compact adjacent layout of the test signal access region and signal access region in the planar direction while introducing vertical separation through different pin heights. This allows the device to benefit from reduced area while simultaneously protecting against damage by utilizing the third dimension (height) to create physical separation between the pin types.
Solution Approach 2:
The patent applies different local qualities to the two pin types by positioning the test signal access pin at a different height and providing it with dedicated insulating layer protection. This localized differentiation allows the test probe to safely contact the test pin without risking damage to the signal access pin, even though both regions are adjacent in the planar layout.
Data Source
AI summary
A display substrate includes an underlay substrate, a test signal access pin layer, and a signal access pin layer. The underlay substrate includes a display region and a border region at a periphery of the display region. The border region includes a signal access region at one side of the display region and at least one test signal access region adjacent to the signal access region. The test signal access pin layer is in the at least one test signal access region. The signal access pin layer is in the signal access region. A height difference between a surface of the test signal access pin layer away from the underlay substrate and a surface of the signal access pin layer away from the underlay substrate is greater than 0.