Display Pipe Alternate Cache Hint for Video Memory
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Solution Overview
Problem
The inefficiencies in data allocation within a memory hierarchy, particularly in systems with multiple sources accessing caches, lead to increased memory latency and power consumption due to conflict misses and data eviction, especially in scenarios like video processing in smartphones or tablets where multiple sources compete for cache storage.
Innovation Solution
Implementing a semiconductor chip with a memory controller and display controller that uses cache hint information to dynamically decide whether to store video frame data in an on-die cache or off-die SDRAM, alternating based on parameters N and M for consecutive memory access requests, optimizing for power-performance tradeoffs and cache utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple sources store data in the cache, then data access speed improves, but conflict misses and data eviction increase causing performance degradation
Solution Approach 1:
The patent divides the cache into multiple independent sets, each dedicated to a specific video source. This segmentation prevents conflict misses between different sources by ensuring that each source's data resides in its own designated set, thereby maintaining high cache hit rates while allowing multiple sources to simultaneously utilize the cache without interference.
Solution Approach 2:
The patent implements source-specific cache sets where each set is optimized for a particular video source's access patterns and data characteristics. This local quality approach allows each source to benefit from cache behavior tailored to its specific requirements, improving overall system performance while preventing cross-source conflicts.
2Adaptability or versatility
If data is frequently evicted from cache to make room for other sources, then cache utilization improves, but power consumption increases due to eviction logic and lower-level memory accesses
Solution Approach 1:
By segmenting the cache into source-specific sets, the patent eliminates the need for frequent data eviction between sources. Each source has dedicated storage space, so data remains in cache longer without being displaced by other sources, thereby reducing power consumption associated with eviction operations and lower-level memory accesses.
Solution Approach 2:
The patent pre-allocates specific cache sets to each video source before data storage occurs. This preliminary assignment prevents future conflicts and evictions by ensuring that each source's data has a predetermined home in the cache, avoiding the power-intensive eviction and re-loading operations that would otherwise be necessary.
3Loss of time
If on-die cache is used instead of off-chip memory, then data access latency reduces, but power consumption increases due to cache maintenance and replacement algorithms
Solution Approach 1:
The patent segments the on-die cache into multiple smaller, source-specific sets. This segmentation reduces the overhead of cache maintenance and replacement algorithms by limiting the scope of operations to smaller, dedicated subsets rather than managing a large unified cache, thereby reducing power consumption while maintaining the low latency benefits of on-die storage.
Solution Approach 2:
The patent implements partial caching by allocating only specific portions of the on-die cache to each video source based on their individual needs. This partial action approach allows the system to benefit from fast on-die access for frequently used data while avoiding the full power consumption cost of maintaining a large unified cache, achieving an optimal balance between latency and power usage.
Data Source
AI summary
A system and method for efficiently allocating data in a memory hierarchy. A system includes a memory controller for controlling accesses to a memory and a display controller for processing video frame data. The memory controller includes a cache capable of storing data read from the memory. A given video frame may be processed by the display controller and presented on a respective display screen. During processing, control logic within the display controller sends multiple memory access requests to the memory controller with cache hint information. For the frame data, the cache hint information may alternate between (i) indicating to store frame data read in response to respective requests in the memory cache and (ii) indicating to not store the frame data read in response to respective requests in the memory cache.