Display Pipe Translation Prefetching for Memory Latency

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Solution Overview

Problem

Virtual memory systems experience increased latency due to translation misses, as caches are finite and may require fetching translation information from memory, leading to inefficiencies in memory access.

Innovation Solution

Incorporating prefetching translation units in the display pipe that maintain translations in a FIFO fashion, allowing for proactive invalidation and prefetching of contiguous translations, thereby reducing the likelihood of translation misses and optimizing memory access patterns.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If translation caching is implemented in the display pipe, then memory access speed is improved, but translation misses occur when the cache is finite and requires fetching from memory

Engineering Contradiction:
Improvememory access speedVSAvoidtranslation miss latency
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The patent applies preliminary action by implementing a translation prefetcher that proactively loads translation entries into the display pipe's translation cache before they are actually needed. The prefetcher monitors memory access patterns and preemptively fetches translations for upcoming memory references, ensuring that when the display pipe needs to access memory, the necessary translations are already cached, thereby eliminating translation misses and reducing latency.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If a complex translation unit is dedicated to an image processor, then image processor translation hit rate is improved, but device complexity increases

Engineering Contradiction:
Improvetranslation hit rateVSAvoidtranslation unit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing the translation unit into separate functional components: a translation prefetcher module and a translation cache module. The prefetcher operates independently to monitor access patterns and preload translations, while the cache stores the actual translation entries. This modular segmentation allows each component to be optimized independently, improving the translation hit rate for the image processor without requiring a completely dedicated complex translation unit, thus managing device complexity effectively.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS8994741B2Streaming translation in display pipe
Publication Date: 2015.03.31 APPLE INC
  • US8994741B2 patent drawing
  • US8994741B2 patent drawing
  • US8994741B2 patent drawing

AI summary

In an embodiment, a display pipe includes one or more translation units corresponding to images that the display pipe is reading for display. Each translation unit may be configured to prefetch translations ahead of the image data fetches, which may prevent translation misses in the display pipe (at least in most cases). The translation units may maintain translations in first-in, first-out (FIFO) fashion, and the display pipe fetch hardware may inform the translation unit when a given translation or translation is no longer needed. The translation unit may invalidate the identified translations and prefetch additional translation for virtual pages that are contiguous with the most recently prefetched virtual page.