Display Pipeline Power Management via Dynamic Interconnect Gating
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Solution Overview
Problem
Current display pipeline power management techniques do not effectively balance power savings with performance, as they often require complex and resource-intensive methods to manage power consumption during graphics operations.
Innovation Solution
Implementing a power management system that dynamically adjusts the power state of circuits within the display pipeline based on the frequency of image source line fetching, where individual lines are fetched frequently during scaling operations and blocks are fetched less frequently, allowing for power reduction and restoration of idle circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If circuits are powered down to save power, then energy consumption is reduced, but performance may be compromised when power is needed
Solution Approach 1:
The system dynamically adjusts the power state of circuits based on real-time operational needs. Circuits are powered down during idle periods and powered up when needed, creating a dynamic power management system that adapts to varying workload demands rather than maintaining a static power state
Solution Approach 2:
The power management operates periodically by monitoring circuit idle states and toggling power states at appropriate intervals. The system enters low-power mode during idle periods and transitions back to active mode when work is pending, creating a rhythmic pattern of power savings that maintains performance
2Productivity
If individual image source lines are fetched frequently during scaling operations, then scaling performance is maintained, but power consumption increases
Solution Approach 1:
The system segments the image processing workload by separating scaling operations from non-scaling operations. During scaling operations, individual lines are fetched to maintain performance, while during non-scaling operations, block fetching is used to reduce power consumption, allowing the system to optimize for each operational mode independently
Solution Approach 2:
The system changes the fetching parameter (individual lines vs. blocks) based on the operational mode. When scaling is detected, the system switches to individual line fetching with higher frequency; when scaling is not performed, it switches to block fetching with lower frequency, thereby adjusting the parameter to match performance requirements
3Use of energy by moving object
If blocks of image source lines are fetched less frequently, then power savings are achieved, but data transfer efficiency may be reduced
Solution Approach 1:
The system performs preliminary action by pre-fetching blocks of image source lines during non-scaling operations when power savings are prioritized. This allows the display buffer to be populated in advance, reducing the frequency of data transfer operations and thereby reducing overall power consumption while maintaining adequate data supply
Data Source
AI summary
Techniques are disclosed relating to power management within an integrated circuit. In one embodiment, a display buffer receives image data through a data transfer interconnect. A data transfer interconnect is powered down based on the received image data being greater than a threshold amount of data. The display buffer transmits at least a portion of the image data to one or more outputs, and in response to the transmitting, the data transfer interconnect is powered up. In some embodiments, the display buffer includes a plurality of line buffers, each configured to store a respective image source line. In such an embodiment, a display pipe configured to render images to be displayed includes the display buffer, and the powering down is performed in response to the received image data including two or more image source lines.