Display Pipeline Memory Request Aggregation for Power Reduction
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Solution Overview
Problem
Semiconductor chips with multiple functional units face performance bottlenecks and increased power consumption due to repeated overhead processing of memory access requests, preventing the memory subsystem from entering a low-power mode.
Innovation Solution
Implementing a display controller with internal pixel-processing pipelines that aggregates memory requests during idle states, allowing the memory controller to transition to a low-power mode by delaying memory access requests until a programmable threshold is reached, thereby reducing unnecessary memory accesses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple functional units send individual memory access requests to the memory controller, then each source can access memory independently, but the repeated overhead processing creates a performance bottleneck and increases power consumption
Solution Approach 1:
The patent merges multiple individual memory access requests from different functional units into a single aggregated request. The display controller combines requests from multiple display pipelines into one unified request stream to the memory controller, eliminating repeated overhead processing and reducing power consumption while maintaining memory access functionality.
2Device complexity
If burst mode is used to reduce the number of individual requests, then overhead processing is reduced, but the memory subsystem cannot enter low-power mode because requests continue to be sent
Solution Approach 1:
The patent implements periodic action by enabling the memory subsystem to alternate between active and low-power states. During idle periods when no display refresh is needed, the system enters low-power mode. Requests are sent periodically only when necessary for display updates, allowing the memory subsystem to remain in low-power state longer while still meeting display refresh requirements.
3Reliability
If display pipelines continuously access shared memory to maintain display refresh, then display functionality is maintained, but other functional blocks cannot utilize the memory subsystem during idle times
Solution Approach 1:
The patent applies dynamics by making the memory access pattern adaptive rather than static. The system dynamically adjusts between continuous access and low-power modes based on actual display refresh needs. When displays are idle or already refreshed, access is reduced or suspended, allowing other functional blocks to utilize the memory subsystem. When display refresh is needed, access resumes to maintain display functionality.
Data Source
AI summary
A system and method for efficiently scheduling memory access requests. A semiconductor chip includes a memory controller for controlling accesses to a shared memory and a display controller for processing frame data. In response to detecting an idle state for the system and the supported one or more displays, the display controller aggregates memory requests for a given display pipeline of one or more display pipelines prior to attempting to send any memory requests from the given display pipeline to the memory controller. Arbitration may be performed while the given display pipeline sends the aggregated memory requests. In response to not receiving memory access requests from the functional blocks or the display controller, the memory controller may transition to a low-power mode.